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publication release date: may 16, 2007 - 1 - revision 1.4 isd5100 series single-chip 1 to 16 minutes duration voice record/playback devices with digital storage capability
isd5100 series - 2 - 1. general description the isd5100 chipcorder ? series provide high quality, fully integrated, single-chip record/playback solutions for 1- to 16-minute messaging applicat ions that are ideal for use in cellular phones, automotive communications, gps/navigation systems and other portable products. the isd5100 series products are an enhancement of the isd5000 architecture, providing: 1) the i 2 c serial port - address, control and duration selection are accomplished through an i 2 c interface to minimize pin count (only two co ntrol lines required); 2) the capability of st oring digital data, in addition to analog data. this feature allows customers to store phone numbers, system configuration parameters and message address locations for message management capability; 3) various internal circuit blocks can be individually powered-up or -down for power saving. the isd5100 series include: ? isd5116 from 8 to 16 minutes ? isd5108 from 4 to 8 minutes ? isd5104 from 2 to 4 minutes ? isd5102 from 1 to 2 minutes analog functions and audio gating have also been integrated into the isd5100 series products to allow easy interface with integrated digital cellular chip sets on the market. audio paths have been designed to enable full duplex conversation record, voice memo, answering machine (including outgoing message playback) and call screening features. this product enables playback of messages while the phone is in standby, and both simplex and duplex playback of messages while on a phone call. additional voice storage features for digital cellular phones include: 1) a personalized outgoing message can be sent to the person by getting caller-id information from the host chipset, 2) a private call announce while on call can be heard from the host by giving caller-id on call waiting information from the host chipset. logic interface options of 2.0v and 3.0v are supported by the isd5100 series to accommodate portable communication products (2.0- and 3.0-volt required). like other chipcorder ? products, the isd5100 series integrate the sampling clock, anti-aliasing and smoothing filters, and the multi-level storage array on a single-chip. for enh anced voice features, the isd5100 series eliminate external circuitry by integrating automatic gain control (agc), a power amplifier/speaker driver, volume co ntrol, summing amplifiers, analog sw itches, and a car kit interface. input level adjustable amplifiers are also include d, providing a flexible interface for multiple applications. recordings are stored into on-chip nonvolatile memory cells, providing zero-power message storage. this unique, single-chip solution is made possible through winbond?s patented multilevel storage technology. voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality on voice and music reproduction.
isd5100 series publication release date: may 16, 2007 - 3 - revision 1.4 2. features fully-integrated solution ? single-chip voice record/playback solution ? dual storage of digital and analog data ? durations device isd5102 isd5104 isd5108 isd5116 duration 1 to 2 minutes 2 to 4 minutes 4 to 8 minutes 8 to 16 minutes low power consumption ? supply voltage ? commercial temperature = +2.7v to +3.3v ? industrial temperature = +2.7v to +3 .3v (+2.7v to +3.6v for isd5108 only) ? supports 2.0v and 3.0v interface logic ? operating current: ? i cc play = 15 ma (typical) ? i cc rec = 30 ma (typical) ? i cc feedthrough = 12 ma (typical) ? standby current: ? i sb = 1 a (typical) ? most stages can be individually powered down to minimize power consumption enhanced voice features ? one or two-way conversation record ? one or two-way message playback ? voice memo record and playback ? private call screening ? in-terminal answering machine ? personalized outgoing message ? private call announce while on call digital memory features device isd5102 isd5104 isd5108 isd5116 storage up to 512kb up to 1 mb up to 2 mb up to 4 mb ? storage of phone numbers, system configuration para meters and message address table in some application easy-to-use and control ? no compression algorithm development required ? user-controllable sampling rates ? programmable analog interface ? standard & fast mode i 2 c serial interface (100khz ? 400 khz) ? fully addressable for multiple messages high quality solution ? high quality voice and music reproduction ? winbond?s standard 100-year message retention (typical) ? 100k record cycles (typical) for analog data ? 10k record cycles (typical) for digital data options ? available in die form, tsop and soic and pdip (isd5116 only) ? temperature: commercial ? packaged (0 to +70c) & die (0 to +50c); industrial (-40 to +85c) ? pb-free package
isd5100 series - 4 - 3. block diagram isd5100-series block diagram aux in amp 1.0 / 1.4 / 2.0 / 2.8 agc sum1 mux vol mux filter mux low pass filter sum1 fthru inp ana out mux vol sum2 ana in vol sp+ sp- speaker aux out ana out- ana out+ mic+ mic - agccap microphone aux in xclk ana in v ssa v cca v ssa v ssd v ssd v ccd v ccd 64-bit/samp. array output mux array input mux input source mux array i/o mux filto sum1 inp ana in sum2 filto sum2 sum1 summing amp ana in amp 0.625/0.883/1.25/1.76 6db sum2 summing amp output mux volume control mic in aux in filto ana in sum1 ana in filto sum2 (analog) array inp sum1 mux ctrl (digital) 64-bit/samp. array out (analog) array out (digital) array spkr . amp aux out amp power conditioning rac int sda scl a1 a0 device control internal clock multilevel/digital storage array ana out amp 2 ( ) vls0 vls1 2 ( ) aig0 aig1 2 ( ) axg0 axg1 2 ( ) s1s0 s1s1 2 ( ) s1m0 s1m1 2 ( ) s2m0 s2m1 ( ) opa0 opa1 2 ( ) ops0 ops1 2 ( ) fld0 fld1 2 (ins0) 1 1 (axpd) 1 (agpd) 1 (flpd) 1 (fls0) 1 (aipd) 1 (aopd) ( ) 3 aos0 aos1 aos2 3 ( ) vol0 vol1 vol2 1 (v lpd )
isd5100 series publication release date: may 16, 2007 - 5 - revision 1.4 4. table of contents 1. general description......................................................................................................... ..........2 2. features .................................................................................................................... ......................3 3. block diagram............................................................................................................... ...............45 4. table of contents ........................................................................................................... ..........56 5. pin configuration ........................................................................................................... .........712 6. pin description ............................................................................................................. .............813 7. functional description...................................................................................................... ...915 7.1. overview .................................................................................................................. ..................915 7.1.1 speech/voice quality..................................................................................................... ......915 7.1.2. duration................................................................................................................ ...............915 7.1.3. flash technology........................................................................................................ ........915 7.1.4. microcontroller interface............................................................................................... .......915 7.1.5. programming............................................................................................................. ........1016 7.2. functional details ........................................................................................................ ............1016 7.2.1. internal registers ...................................................................................................... ........1117 7.2.2. memory architecture ..................................................................................................... ....1117 7.3. operational modes description .............................. ............................................................... ..1218 7.3.1. i 2 c interface .................................................................................................................... ..1218 7.3.2. i 2 c control registers ........................................................................................................1622 7.3.3. opcode su mmary .......................................................................................................... ...1723 7.3.4. data bytes.............................................................................................................. ...........1925 7.3.5. configuration register bytes ............................................................................................ 2026 7.3.6. power-up sequence....................................................................................................... ...2127 7.3.7. feed through mode....................................................................................................... ...2228 7.3.8. call record............................................................................................................. ...........2430 7.3.9. memo record............................................................................................................. .......2531 7.3.10. memo and call playback ................................................................................................2 632 7.3.11. message cueing ......................................................................................................... ....2733 7.4. analog mode............................................................................................................... .............2834 7.4.1. aux in and ana in description........................................................................................... 2834 7.4.2. isd5100 series analog structur e (left half) description...................................................2935 7.4.3. isd5100 series aanalo g structure (right half) description ..... .........................................3036 7.4.4. volume control description .............................................................................................. 3137 7.4.5. speaker and aux out description.....................................................................................3238
isd5100 series - 6 - 7.4.6. ana out description ..................................................................................................... .....3339 7.4.7. analog inputs ........................................................................................................... .........3339 7.5. digital mode .............................................................................................................. ...............3642 7.5.1. erasing digital data .................................................................................................... ......3642 7.5.2. writing digital data .................................................................................................... .......3642 7.5.3. reading digital data .................................................................................................... .....3743 7.5.4. example command sequ ences .......................................................................................3743 7.6. pin details............................................................................................................... .................4854 7.6.1. digital i/o pins........................................................................................................ ...........4854 7.6.2. analog i/o pins ......................................................................................................... ........5057 7.6.3. power and ground pins ................................................................................................... .5462 7.6.4. pcb layout examples ..................................................................................................... .5563 8.1. i 2 c timing diagram............................................................................................................... ...5665 8.2. playback and stop cycle................................................................................................... ......5867 8.3. example of power up command (first 12 bits) ....... ................................................................5968 9. absolute maximum ratings.................................................................................................606 9 10. electrical characteristics ............................................................................................6271 10.1. general parameters ....................................................................................................... .......6271 10.2. timing parameters ........................................................................................................ ........6372 10.3. analog parameters ........................................................................................................ ........6574 10.4. characteristics of the i 2 c serial interface ............................................................................6978 10.5. i 2 c protocol..................................................................................................................... .......7282 11. typical application circuit ..............................................................................................74 84 12. package specification ...................................................................................................... .7586 12.1. 28-lead 8x13.4mm plastic thin small outline package (tsop) type 1 - iqc ...................7586 12.2. 28-lead 8x13.4mm plastic thin small outline pa ckage (tsop) type 1 ...... .............. .........7687 12.3. 28-lead 300-mil plastic small out line integrated circuit (soic)..........................................7788 12.4. 28-lead 600-mil plastic dual inline package (pdip) .. ..........................................................7889 12.5 isd5116 die information.................................................................................................. ....7990 12.6 isd5108 die information.................................................................................................. ....8193 12.7 isd5104 die information.................................................................................................. ....8395 12.8 isd5102 die information.................................................................................................. ....8597 13. ordering information....................................................................................................... .8799 14. version history ............................................................................................................ ......88101
isd5100 series publication release date: may 16, 2007 - 7 - revision 1.4 5. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v ccd v ccd xclk int rac v ssa nc nc aux out aux in ana in v cca sp+ v ssa scl a1 sda a0 v ssd v ssd nc mic+ v ssa mic- ana out+ ana out- acap sp- pdip isd5116 soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v ccd v ccd xclk int rac v ssa nc nc aux out aux in ana in v cca sp+ v ssa scl a1 sda a0 v ssd v ssd nc mic+ v ssa mic- ana out+ ana out- acap sp- isd5116 isd5108 isd5104 isd5102 tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc aux out aux in ana in v cca sp+ v ssa sp- acap ana out- ana out+ mic- mic+ v ssa nc v ssa rac int xclk v ccd v ccd scl a1 sda a0 v ssd v ssd nc isd5116 isd5108 isd5104 isd5102
isd5100 series - 8 - 6. pin description pin name soic/pdip tsop functionality scl 1 8 i 2 c serial clock line: to clock th e data into and out of the i 2 c interface. a1 2 9 input pin that supplies the lsb +1 bit for the i 2 c slave address. sda 3 10 i 2 c serial data line: data is passed between devices on the bus over this line. a0 4 11 input pin that supplies the lsb for the i 2 c slave address. v ssd 5,6 12,13 digital ground. nc 7,21,22 1,14,28 no connect. mic+ 8 16 differential positive input for the microphone amplifier. v ssa 9,15,23 2,15,22 analog ground. mic- 10 17 differential negative input for the microphone amplifier. ana out+ 11 18 differential positive analog output for ana out. ana out- 12 19 differential negati ve analog output for ana out. acap 13 20 agc/automute capacitor: required for the on-chip agc amplifier during record and automute function during playback. sp- 14 21 differential negative speaker output: when the speaker outputs are in use, the aux out output is disabled. sp+ 16 23 differential po sitive speaker output. v cca 17 24 analog supply voltage: this pin supplies power to the analog sections of the device. it should be carefully bypassed to analog ground to insure correct de vice operation. ana in 18 25 analog input: one of th e analog inputs with selectable gain. aux in 19 26 auxiliary input: one of the analog inputs with selectable gain. aux out 20 27 auxiliary out put: one the analog outputs of the device. when this output is used, the sp+ and sp- outputs are disabled. rac 24 3 row address clock; an open drain output. the rac pin goes low t racl [1] before the end of each row of memory and returns high at exactly the end of ea ch row of memory. int 25 4 interrupt output; an open drain output that indicates that a set eom bit has been found during playback or that the chip is in an overflow (ovf) condition. this pin remains low until a read status command is executed. xclk 26 5 this pin must be grounded for utilizing internal clock. for precision timing control, external clock signal can be applied through this pin. v ccd 27,28 6,7 digital supply voltage. these pins supply power to the digital sections of the device. they must be carefully bypassed to digital ground to insure correct de vice operation. [1] see the parameters section
isd5100 series publication release date: may 16, 2007 - 9 - revision 1.4 7. functional description 7.1. o verview 7.1.1 speech/voice quality the isd5100 chipcorder series can be configured via software to operate at 4.0, 5.3, 6.4 or 8.0 khz sampling frequency to select appropriate voice quality. increasing the duration decreases the sampling frequency and bandwidth, which affects audio quality. the table in the following section shows the relationship between sampling frequency, duration and filter pass band. 7.1.2. duration to meet system requirements, the isd5100 series are single-chip solution, which provide 1 to 16 minutes of voice record and playback, depending upon the sample rates chosen. duration [1] sample rate (khz) isd5116 isd5108 isd5104 isd5102 typical filter knee (khz) 8.0 8 min 44 sec 4 min 22 sec 2 min 11 sec 1 min 5 sec 3.4 6.4 10 min 55 sec 5 min 27 sec 2 min 43 sec 1 min 21 sec 2.7 5.3 13 min 6 sec 6 min 33 sec 3 min 17 sec 1 min 38 sec 2.3 4.0 17 min 28 sec 8 min 44 sec 4 min 22 sec 2 min 11 sec 1.7 [1] minus any pages selected for digital storage 7.1.3. flash technology one of the benefits of winbond?s chipcorder technology is the use of on-chip flash memory, which provides zero-power message storage. the message is retained for up to 100 years (typically) without power. in addition, the device can be re-recorded over 10,000 times (typically) for the digital data and over 100,000 times (typically) for the analog messages. a new feature has been added that allows memory space in the isd5100 series to be allocated to either digital or analog storage when recorded. t he fact that a section has been assigned digital or analog data is stored in the message address table by the system microcontroller when the recording is made. 7.1.4. microcontroller interface the isd5100 series are controlled through an i 2 c 2-wire interface. this synchronous serial port allows commands, configurations, address data, and digital data to be loaded into the device, while allowing status, digital data and current address information to be read back from the device. in addition to the serial interface, two other status pins can feedback to the microcontroller for enhanced
isd5100 series - 10 - interface. these are the rac timing pin and the int pin for interrupts to the controller. communications with all the internal registers of any operations are through the serial bus, as well as digital memory read and write operations. 7.1.5. programming the isd5100 series are also ideal for playback-only applications, where single or multiple messages may be played back when desired. playback is controlled through the i 2 c interface. once the desired message configuration is created, duplicates can easily be generated via a third-party programmer. for more information on available application tools and programmers, please see the winbond web site at www.winbond-usa.com 7.2. f unctional d etails the isd5100 series are single chip solutions for analog and digital data storage. the array can be divided between analog and digital storage according to user?s choice, when the device is configured. the below block diagram shows that the isd5116 device can be easily designed into a telephone answering machine (tad). both mic inputs transmit the voice input signal from the microphone to perform ogm recording, as well as to record the speech during phone conversation (simplex). when the tad is activated, the voice of the other party from the phone line feeds into the aux in, and is recorded into the isd5116 device. then the new messge is usually indicated with blinking new message led. hence, during playback, the recorded message is sent out to speaker with volume control. two i 2 c pins are used for all communications between the chipcorder and the microcontroller for analog and/or digital storage, and the two outputs, int and rac are feedback to microcontroller for message management. for duplex recording, speech from mic inputs and message from received path can be directly recorded into the array simultaneously, then playback afterwards. in addition, for speaker phone speaker isd5116 sp+ sp- mic+ mic- microcontroller i 2 c (int, rac) nv memory display & push buttons aux in aux out daa phone line dtmf detect, caller id a na out+
isd5100 series publication release date: may 16, 2007 - 11 - revision 1.4 operation, voice from mic inputs are fed to aux out and transmitted to the phone line, while message from other party is input from the aux in, then fed through to the speaker for listening. the isd5100 device has the flexib ility for other applications, be cause the audio paths can be configured differently, with each circuit block being powered-up or ?down individually, according to the applications requirement. 7.2.1. internal registers the isd5100 series have multiple internal registers that are used to store the address information and the configuration or set-up of the device. the two 16-bit configuration registers control the audio paths through the device, the sample frequency, the various gains and attenuations, power up and down of different sections, and the volume settings. these registers are discussed in detail in section 7.3.5 . 7.2.2. memory architecture the isd5100 series memory array are arranged in various pages (or rows) of each 2048 bits as follows. the primary addressing for the pages are handled by 11 bits of address input in the analog mode. a memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. the contents of a page are either analog or digital. this is determined by instruction (opcode) at the time the data is written. a record of where is analog and where is digital, is stored in a message address table (mat) by the system microcontroller. the mat is a table kept in the microcontroller memory that defines the status of each message ?page?. it can be stored back into the isd5100 series if the power fails or the system is turned off. using this table allows efficient message management. segments of messages can be stored wherever there is available space in the memory array. [this is explained in detail for the isd5008 in app lications note #9 and w ill be similarly described in a later note for the isd5100-series.] products pages (rows) bits/page memory size isd5116 2048 2048 4,194,304 bits isd5108 1024 2048 2,097,152 bits isd5104 512 2048 1,048,576 bits isd5102 256 2048 524,288 bits when a page is used for analog storage, the same 32 blocks are present but there are 8 eom (end- of-message) markers. this means that for each 4 blocks there is an eom marker at the end. thus, when recording, the anal og recording will stop at any one of eight positions. at 8 khz sampling frequency, this results in a resolution of 32 msec when ending an analog recording. beginning an analog recording is limited to the 256 msec resolution provided by the 11-bit address. a recording does not immediately stop when the stop command is given, but continues until the 32 millisecond block is filled. then a bit is placed in the eom memory to develop the interrupt that signals a message is finished playing in the playback mode.
isd5100 series - 12 - digital data is sent and received serially over the i 2 c interface. the data is serial-to-parallel converted and stored in one of two alternating (commutating) 64-bit shift registers. when an input register is full, it becomes the register that is pa rallel written into the array. the pr ior write register becomes the new serial input register. a mechanism is built-in to ensure there is always a register available for storing new data. storing data in the memory is accomplished by accepting data one byte at a time and issuing an acknowledge. if data is coming in faster than it can be written, the chip issues an acknowledge to the host microcontroller, but holds scl low until it is ready to accept more data. (see section 7.5.2 for details). the read mode is the opposite of the write mode. data is read into one of two 64-bit registers from the array and serially sent to the i 2 c interface. (see section 7.5.3 for details). 7.3. o perational m odes d escription 7.3.1. i 2 c interface to use more than four isd5100 series devices in an application requires some external switching of the i 2 c interface. i 2 c interface important note: the rest of this data shee t will assume that the reader is familiar with the i 2 c serial interface. additional information on i 2 c may be found in section 10 on page 72 of this document. if you are not familiar with this se rial protocol, please read this section to familiarize yourself with it. a large amount of additional information on i 2 c can also be found on the philips web page at http://www.philips.com/ . i 2 c slave address the isd5100 series have 7-bit slave address of <100 00xy> where x and y are equal to the state, respectively, of the external address pins a1 and a0. because all data bytes are required to be 8 bits, the lsb of the address byte is the read/write se lection bit that tells the slave whether to transmit or receive data. therefore, there are 8 possible slave addresses for the isd5100-series. these are:
isd5100 series publication release date: may 16, 2007 - 13 - revision 1.4 pinout table a1 a0 slave address r/w bit hex value 0 0 <100 0000> 0 80 0 1 <100 0001> 0 82 1 0 <100 0010> 0 84 1 1 <100 0011> 0 86 0 0 <100 0000> 1 81 0 1 <100 0001> 1 83 1 0 <100 0010> 1 85 1 1 <100 0011> 1 87 isd5100 series i 2 c operation definitions there are many control functions used to operate the isd5100-series. among them are: 7.3.1.1. read status command: the read status command is a read request from the host processor to the isd5100 series without delivering a command byte. the host supplies all the clocks (scl). in each case, the entity sending the data drives the data line (sda). the read status command is executed by the following i 2 c sequence. 1. host executes i 2 c start 2. send slave address with r/w bit = ?1? (read) 81h 3. slave (isd5100-series) responds back to host an acknowledge (ack) followed by 8-bit status word 4. host sends an acknowledge (ack) to slave 5. wait for scl to go high 6. slave responds with upper address byte of internal address register 7. host sends an ack to slave 8. wait for scl to go high 9. slave responds with lower address byte of inte rnal address register (a[4:0] will always return set to 0.) 10. host sends a no ack to slave, then executes i 2 c stop
isd5100 series - 14 - note that the processor could have sent an i 2 c stop after the status word data transfer and aborted the transfer of the address bytes. a graphical representation of this operation is found below. see the caption box above for more explanation. s slave address a a data p r data data a n status hi g h addr. low addr. conventions used in i 2 c data transfer diagrams = start condition = stop condition = 8-bit data transfer = ?1? in the r/w bit = ?0? in the r/w bit = ack (acknowledge) = no ack s slave address a data p = host to slave (gray) = slave to host (white) the box color indicates the direction of data flow = 7-bit slave address n r w
isd5100 series publication release date: may 16, 2007 - 15 - revision 1.4 7.3.1.2. load command byte register (single byte load): a single byte may be written to the command byte register in order to power up the device, start or stop analog record (if no address information is needed), or do a message cueing function. the command byte register is loaded as follows: 1. host executes i 2 c start 2. send slave address with r/w bit = ?0? (write) [80h] 3. slave responds back with an ack. 4. wait for scl to go high 5. host sends a command byte to slave 6. slave responds with an ack 7. wait for scl to go high 8. host executes i 2 c stop 7.3.1.3. load command byte register (address load) for the normal addressed mode the registers are loaded as follows: 1. host executes i 2 c start 2. send slave address with r/w bit = ?0? (write) 3. slave responds back with an ack. 4. wait for scl to go high 5. host sends a byte to slave - (command byte) 6. slave responds with an ack 7. wait for scl to go high 8. host sends a byte to slave - (high address byte) 9. slave responds with an ack 10. wait for scl to go high 11. host sends a byte to slave - (low address byte) 12. slave responds with an ack 13. wait for scl to go high 14. host executes i 2 c stop s slave address a data p w command byte a s slave address a p w command data a data a data a hi g h addr. low addr.
isd5100 series - 16 - 7.3.2. i 2 c control registers the isd5100 series are controlled by loading commands to, or, reading from, the internal command, configuration and address registers. the command byte sent is used to start and stop recording, write or read digital data and perform other functions necessary for the operation of the device. command byte control of the isd5100 series are implemented through an 8-bit command byte, sent after the 7-bit device address and the 1-bit read/write selection bit. the 8 bits are: ? global power up bit ? dab bit: determines whether device is performing an analog or digital function ? 3 function bits: these determine which function the device is to perform in conjunction with the dab bit. ? 3 register address bits: these determine if and when data is to be loaded to a register c7 c6 c5 c4 c3 c2 c1 c0 pu dab fn2 fn1 fn0 rg2 rg1 rg0 function bits register bits function bits the command byte function bits are detailed in the table to the right. c6, the dab bit, determines whether the device is performing an analog or digital function. the other bits are decoded to produce the individual commands. not all decode combinations are currently used, and are reserved for future use. out of 16 possible codes, the isd5100 series uses 7 for normal operation. the other 9 are undefined function bits c6 c5 c4 c3 dab fn2 fn1 fn0 function 0 0 0 0 stop (or do nothing) 0 1 0 1 analog play 0 0 1 0 analog record 0 1 1 1 analog mc 1 1 0 0 digital read 1 0 0 1 digital write 1 0 1 0 erase (row) power up bit
isd5100 series publication release date: may 16, 2007 - 17 - revision 1.4 register bits the register load may be used to modify a command sequence (such as load an address) or used with the null command sequence to load a configuration or test register. not all registers are accessible to the user. [rg2 is always 0 as the four additional combinations are undefined.] 7.3.3. opcode summary opcode command description the following commands are used to access the chip through the i 2 c interface. ? play: analog play command ? record: analog record command ? message cue: analog message cue command ? read: digital read command ? write: digital write command ? erase: digital page and block erase command ? power up: global power up/down bit. (c7) ? load cfg0: load configuration register 0 ? load cfg1: load configuration register 1 ? read status: read the interrupt status and address register, including a hardwired device id rg2 rg1 rg0 c2 c1 c0 function 0 0 0 no action 0 0 1 reserved 0 1 0 load cfg0 0 1 1 load cfg1
isd5100 series - 18 - opcode command byte table pwr function bits register bits opcode hex pu dab fn2 fn1 fn0 rg2 rg1 rg0 command bit number cmd c7 c6 c5 c4 c3 c2 c1 c0 power up 80 1 0 0 0 0 0 0 0 power down 00 0 0 0 0 0 0 0 0 stop (do nothing) stay on 80 1 0 0 0 0 0 0 0 stop (do nothing) stay off 00 0 0 0 0 0 0 0 0 load cfg0 82 1 0 0 0 0 0 1 0 load cfg1 83 1 0 0 0 0 0 1 1 record analog 90 1 0 0 1 0 0 0 0 record analog @ addr 91 1 0 0 1 0 0 0 1 play analog a8 1 0 1 0 1 0 0 0 play analog @ addr a9 1 0 1 0 1 0 0 1 msg cue analog b8 1 0 1 1 1 0 0 0 msg cue analog @ addr b9 1 0 1 1 1 0 0 1 enter digital mode c0 1 1 0 0 0 0 0 0 exit digital mode 40 0 1 0 0 0 0 0 0 digital erase page d0 1 1 0 1 0 0 0 0 digital erase page @ addr d1 1 1 0 1 0 0 0 1 digital write c8 1 1 0 0 1 0 0 0 digital write @ addr c9 1 1 0 0 1 0 0 1 digital read e0 1 1 1 0 0 0 0 0 digital read @ addr e1 1 1 1 0 0 0 0 1 read status 1 n/a n/a n/a n/a n/a n/a n/a n/a n/a 1. see section 7.2 on page 12 for details.
isd5100 series publication release date: may 16, 2007 - 19 - revision 1.4 7.3.4. data bytes in the i 2 c write mode, the device can accept data sent after the command byte. if a register load option is selected, the next two bytes are loaded into the selected register. the format of the data is msb first, the i 2 c standard. thus to load data<15:0> into the device, data<15:8> is sent first, the byte is acknowledged, and data<7:0> is sent next. the address register consists of two bytes. the format of the address is as follows: address<15:0> = page_address<10:0>, block_address<4:0> note: if an analog function is selected, the block address bits must be set to 00000. digital read and write are block addressable. when the device is polled with the read status command, it will retu rn three bytes of data. the first byte is the status byte, the next the upper address byte and the last the lower address byte. the status register is one byte long and its bit function is: status<7:0> = eom, ovf, ready, pd, prb, device_id<2:0> lower address byte will always return the block addres s bits as zero, either in digital or analog mode. the functions of the bits are: eom bit 7 indicates whether an eom interrupt has occurred. ovf bit 6 indicates whether an overflow interrupt has occurred. ready bit 5 indicates the internal status of the device ? if ready is low no new commands should be sent to device, i.e. not ready. pd bit 4 device is powere d down if pd is high. prb bit 3 play/record mode indicator. high=play/low=record. device_id bit 0, 1, 2 a n internal device id. isd5116 = 001; isd5108 = 010; isd5104 = 100 and isd5102 = 101. it is recommended that you read the status register after a write or record operation to ensure that the device is ready to accept new commands. depending upon the design and the number of pins available on the controller, the po lling overhead can be reduced. if int and rac are tied to the microcontroller, it does not have to poll as frequently to determine the status of the isd5100-series.
isd5100 series - 20 - 7.3.5. configuration register bytes the configuration register bytes are defined, in detail, in the drawings of section 7.4 on page 29. the drawings display how each bit enables or disables a function of the audio paths in the isd5100- series. the tables below give a general illustration of the bits. there are two configuration registers, cfg0 and cfg1, so there are four 8-bit bytes to be loaded during the set-up of the device. d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 configuration register 0 (cfg0) aig1 aig0 aipd axg1 axg0 axpd ins0 aos2 aos1 aos0 aopd ops1 ops0 opa1 opa0 vlpd volume control power down spkr & aux out control (2 bits) output mux select (2 bits) ana out power down auxout mux select (3 bits) input source mux select (1 bit) aux in power down aux in amp gain set (2 bits) ana in power down ana in amp gain set (2 bits) d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 configuration register 0 (cfg0) aig1 aig0 aipd axg1 axg0 axpd ins0 aos2 aos1 aos0 aopd ops1 ops0 opa1 opa0 vlpd volume control power down spkr & aux out control (2 bits) output mux select (2 bits) ana out power down auxout mux select (3 bits) input source mux select (1 bit) aux in power down aux in amp gain set (2 bits) ana in power down ana in amp gain set (2 bits)
isd5100 series publication release date: may 16, 2007 - 21 - revision 1.4 agc amp power down filter power down sample rate (& filter) set up (2 bits) filter mux select sum 2 summing amp control (2 bits) sum 1 summing amp control (2 bits) sum 1 mux select (2 bits) volume control (3 bits) volume cont. mux select (2 bits) configuration register 1 (cfg1) vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 agc amp power down filter power down sample rate (& filter) set up (2 bits) filter mux select sum 2 summing amp control (2 bits) sum 1 summing amp control (2 bits) sum 1 mux select (2 bits) volume control (3 bits) volume cont. mux select (2 bits) configuration register 1 (cfg1) vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0 7.3.6. power-up sequence this sequence prepares the isd5100 series for an operation to follow, waiting the tpud time before sending the next command sequence. 1. send i 2 c power up 2. send one byte 10000000 {slave address, r/w = 0} 80h 3. slave ack 4. wait for scl high 5. send one byte 10000000 {command byte = power up} 80h 6. slave ack 7. wait for scl high 8. send i 2 c stop playback mode the command sequence for an analog playback operation can be handled several ways. the most straightforward approach would be to incorporate a single four byte exchange, which consists of the slave address (80h), the command byte (a9h) for play analog @ address, and the two address bytes.
isd5100 series - 22 - record mode the command sequence for an analog record would be a four byte sequence consisting of the slave address (80h), the command byte (91h) for record analog @ address, and the two address bytes. see ?load command byte register (address load)? in section 7.3.2 on page 17. 7.3.7. feed through mode the previous examples were dependent upon the device already being powered up and the various paths being set through the device for the desired operation. to set up the device for the various paths requires loading the two 16-bit configuration registers with the correct data. for example, in the feed through mode the device only needs to be powered up and a few paths selected. this mode enables the isd5100 series to connect to a cellular or cordless base band phone chip set without affecting the audio source or destination. there are two paths involved, the transmit path and the receive path. the transmit path connects the winbond chip?s microphone source through to the microphone input on the base band chip set. the receive path connects the base band chip set?s speaker output through to the speaker driver on the winbond chip. this allows the winbond chip to substitute for those functions and incidentally gain access to the audio to and from the base band chip set. to set up the environment described above, a series of commands need to be sent to the isd5100- series. first, the chip needs to be powered up as described in this section. then the configuration registers must be filled with the specific data to co nnect the paths desired. in the case of the feed through mode, most of the chip can remain powe red down. the following figure illustrates the affected paths. the figure above shows the part of the isd5100 series block diagram that is used in feed through mode. the rest of the chip will be powered down to conserve power. the bold lines highlight the audio paths. note that the microphone to ana out +/? path is differential. microphone mic+ mic- chip set ana out+ a na ou t - chip set ana in s p eaker sp+ sp- output mux ana in amp 6 db ana out mux fthru inp filt o sum1 sum2 v ol vol filto ana in amp sum2 3 [aos2,aos1,aos0] 1 [aopd] 2 [opa1,opa0] 2 [ops1,ops0] 2 [aig1,aig0] 1 [apd]
isd5100 series publication release date: may 16, 2007 - 23 - revision 1.4 to select this mode, the following control bits must be configured in the isd5100 series configuration registers. to set up the transmit path: 1. select the fthru path through the ana out mux?bits aos0, aos1 and aos2 control the state of the ana out mux. these are the d6, d7 and d8 bits respectively of configuration register 0 (cfg0) and they should all be zero to select the fthru path. 2. power up the ana out amplifier?bit aopd controls the power up state of ana out. this is bit d5 of cfg0 and it should be a zero to power up the amplifier. to set up the receive path: 1. set up the ana in amplifier for the correct gain?bits aig0 and aig1 control the gain settings of this amplifier. these are bits d14 and d15 re spectively of cfg0. the input level at this pin determines the setting of this gain stage. the ana in amplifier gain settings table on page 36 will help determine this setting. in this exam ple, we will assume that the peak signal never goes above 1 volt p-p single ended. that would enable us to use the 9 db attenuation setting, or where d14 is one and d15 is zero. 2. power up the ana in amplifier?bit aipd controls the power up state of ana in. this is bit d13 of cfg0 and should be a zero to power up the amplifier. 3. select the ana in path through the output mux?bits ops0 and ops1 control the state of the output mux. these are bits d3 and d4 respectively of cfg0 and they should be set to the state where d3 is one and d4 is zero to select the ana in path. 4. power up the speaker amplifier?bits opa0 and opa1 control the state of the speaker and aux amplifiers. these are bits d1 and d2 respectively of cfg0. they should be set to the state where d1 is one and d2 is zero. this powers up the speaker amplifier and configures it for its higher gain setting for use with a piezo speaker element and also powers down the aux output stage. the status of the rest of the functions in the isd5100 series chip must be defined before the con- figuration registers settings are updated: 1. power down the volume control element ? bit vlpd controls the power up state of the volume control. this is bit d0 of cfg0 and it should be set to a one to power down this stage. 2. power down the aux in amplifier ? bit axpd controls the power up state of the aux in input amplifier. this is bit d10 of cfg0 and it shou ld be set to a one to power down this stage. 3. power down the sum1 and sum2 mixer amplifiers ? bits s1m0 and s1m1 control the sum1 mixer and bits s2m0 and s2m1 control the sum2 mixer. these are bits d7 and d8 in cfg1 and bits d5 and d6 in cfg1 respectively. all 4 bits should be set to a one to power down these two amplifiers. 4. power down the filter stage ? bit flpd controls the power up state of the filter stage in the device. this is bit d1 in cfg1 and should be set to a one to power down the stage. 5. power down the agc amplifier ? bit agpd controls the power up state of the agc amplifier. this is bit d0 in cfg1 and should be set to a one to power down this stage.
isd5100 series - 24 - 6. don?t care bits ? the following stages are not used in feed through mode. their bits may be set to either level. in this example, we will set all the following bits to a zero. (a). bit ins0, bit d9 of cfg0 controls the input source mux. (b). bits axg0 and axg1 are bits d11 and d12 respectively in cfg0. they control the aux in am plifier gain setting. (c). bits fld0 and fld1 are bits d2 and d3 respectively in cfg1. they control the sample rate and filter band pass setting. (d). bit fls0 is bit d4 in cfg1. it controls the filter mux. (e). bits s1s0 and s1s1 are bits d9 and d10 of cfg1. they control the sum1 mux. (f). bits vol0, vol1 and vol2 are bits d11, d12 and d13 of cfg1. they control the setting of the volume control. (g). bits vls0 and vls1 are bits d14 and d15 of cfg1. they control the volume control mux. the end result of the above set up is cfg0=0100 0100 0000 1011 (hex 440b) and cfg1=0000 0001 1110 0011 (hex 01e3). since both registers are being loaded, cfg0 is loaded, followed by the loading of cfg1. these two registers must be loaded in this order. the internal set up for both registers will take effect synchro- nously with the rising edge of scl. 7.3.8. call record the call record mode adds the ability to record an incoming phone call. in most applications, the isd5100 series would first be set up for feed through mode as described above. when the user wishes to record the incoming call, the setup of the chip is modified to add that ability. for the purpose of this explanation, we will use the 6. 4 khz sample rate during recording. the block diagram of the isd5100 series shows that the multilevel storage array is always driven from the sum2 summing amplifier. the path traces back from there through the low pass filter, the filter mux, the sum1 summing amplifier, the sum1 mux, then from the ana in amplifier. feed through mode has already powered up the ana in amp so we only need to power up and enable the path to the multilevel storage array from that point: 1. select the ana in path through the sum1 mux?bits s1s0 and s1s1 control the state of the sum1 mux. these are bits d9 and d10 respectively of cfg1 and they should be set to the state where both d9 and d10 are zero to select the ana in path. 2. select the sum1 mux input (only) to the s1 summing amplifier?bits s1m0 and s1m1 control the state of the sum1 summing amplifier. these are bits d7 and d8 respectively of cfg1 and they should be set to the state where d7 is one and d8 is zero to select the sum1 mux (only) path. 3. select the sum1 summing amplifier path through the filter mux?bit fls0 controls the state of the filter mux. this is bit d4 of cfg1 and it must be set to zero to select the sum1 summing amplifier path.
isd5100 series publication release date: may 16, 2007 - 25 - revision 1.4 4. power up the low pass filter?bit flpd controls the power up state of the low pass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 5. select the 6.4 khz sample rate ? bits fld0 and fld1 select the low pass filter setting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 6.4 khz sample rate, d2 must be set to one an d d3 set to zero. 6. select the low pass filter input (only) to the s2 summing amplifier ? bits s2m0 and s2m1 control the state of the sum2 summing amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to select the low pass filter (only) path. in this mode, the elements of the original pass through mode do not change. the sections of the chip not required to add the record path remain powered down. in fact, cfg0 does not change and remains cfg0=0100 0100 0000 1011 (hex 440b). cfg1 changes to cfg1=0000 0000 1100 0101 (hex 00c5). since cfg0 is not changed, it is only necessary to load cfg1. note that if only cfg0 was changed, it would be necessary to load both registers. 7.3.9. memo record the memo record mode sets the chip up to record from the local microphone into the chip?s multilevel storage array. a connected cellular telephone or cordless phone chip set may remain powered down and is not active in this mode. the path to be used is microphone input to agc amplifier, then through the input source mux to the sum1 summing amp lifier. from there the path goes through the filter mux, the low pass filter, the sum2 summing amplifier, then to the multilevel storage array. in this instance, we will select the 5.3 khz sample rate. the rest of the chip may be powered down. 1. power up the agc amplifier?bit agpd controls the power up state of the agc amplifier. this is bit d0 of cfg1 and must be set to zero to power up this stage. 2. select the agc amplifier through the input source mux?bit ins0 controls the state of the input source mux. this is bit d9 of cfg0 and must be set to a zero to select the agc amplifier. 3. select the input source mux (only) to the s1 summing amplifier ? bits s1m0 and s1m1 control the state of the sum1 summing amplifier. these are bits d7 and d8 respectively of cfg1 and they should be set to the state where d7 is zero and d8 is one to select the input source mu x (only) path. 4. select the sum1 summing amplifier path through the filter mux?bit fls0 controls the state of the filter mux. this is bit d4 of cfg1 and it must be set to zero to select the sum1 summing amplifier path.
isd5100 series - 26 - 5. power up the low pass filter ? bit flpd controls the power up state of the low pass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 6. select the 5.3 khz sample rate?bits fld0 an d fld1 select the low pass filter setting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 5.3 khz sample rate, d2 must be set to zero and d3 set to one. 7. select the low pass filter input (only) to the s2 summing amplifier ? bits s2m0 and s2m1 control the state of the sum2 summing amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to select the low pass filter (only) path. to set up the chip for memo record, the conf iguration registers are set up as follows: cfg0=0010 0100 0010 0001 (hex 2421). cfg1=0000 0001 0100 1000 (hex 0148). only those portions necessary for this mode are powered up. 7.3.10. memo and call playback this mode sets the chip up for local playback of messages recorded earlier. the playback path is from the multilevel storage array to the filter mux, then to the low pass filter stage. from there, the audio path goes through the sum2 summing amplifier to the volume mux, through the volume control then to the speaker output stage. we will assume that we are driving a piezo speaker element. this audio was previously recorded at 8 khz. all unnecessary stages will be powered down. 1. select the multilevel storage array path through the filter mux ? bit fls0, the state of the filter mux. this is bit d4 of cfg1 and must be set to one to select the multilevel storage array. 2. power up the low pass filter ? bit flpd controls the power up state of the low pass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 3. select the 8.0 khz sample rate?bits fld0 an d fld1 select the low pass filter setting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 8.0 khz sample rate, d2 and d3 must be set to zero. 4. select the low pass filter input (only) to the s2 summing amplifier ?bits s2m0 and s2m1 control the state of the sum2 summing amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to select the low pass filter (only) path. 5. select the sum2 summing amplifier path through the volume mux ? bits vls0 and vls1 control the state volume mux. these bits are bits d14 and d15, respectively of cfg1. they should be set to the state where d14 is one and d15 is zero to select the sum2 summing amplifier.
isd5100 series publication release date: may 16, 2007 - 27 - revision 1.4 6. power up the volume control level ? bit vlpd controls the power-up state of the volume control attenuator. this is bit d0 of cfg0. this bit must be set to a zero to power-up the volume control. 7. select a volume control level?bits vol0, vol1, and vol2 control the state of the volume control level. these are bits d11, d12, and d13, respectively, of cfg1. a binary count of 000 through 111 controls the amount of attenuation through that state. in most cases, the software will select an attenuation level according to the desires of the current users of the product. in this example, we will assume the user wants an attenuation of ?12 db. for that setting, d11 should be set to one, d12 should be set to one, and d13 should be set to a zero. 8. select the volume control path through the output mux ? these are bits d3 and d4, respectively, of cfg0. they should be set to the state where d3 is zero and d4 is a zero to select the volume control. 9. power up the speaker amplifier and select the high gain mode ? bits opa0 and opa1 control the state of the speaker (sp+ and sp?) and aux out outputs. these are bits d1 and d2 of cfg0. they must be set to the state where d1 is one and d2 is zero to power-up the speaker outputs in the high gain mode and to power-down the aux out. to set up the chip for memo or call playback, the configuration registers are set up as follows: cfg0=0010 0100 0010 0100 (hex 2424). cfg1=0101 1001 1101 0001 (hex 59d1). only those portions necessary for this mode are powered up. 7.3.11. message cueing message cueing allows the user to skip through analog messages without knowing the actual physical location of the message. this operation is used during playback. in this mode, the messages are skipped 512 times faster than in normal playback m ode. it will stop when an eom marker is reached. then, the internal address counter will be pointing to th e next message.
isd5100 series - 28 - 7.4. a nalog m ode 7.4.1. aux in and ana in description the aux in is an additional audio input to the isd5100-series, such as from the microphone circuit in a mobile phone ?car kit.? this input has a nominal 694 mv p-p level at its minimum gain setting (0 db). see the aux in amplifier gain settings table on page 37. additional gain is available in 3 db steps (controlled by the i 2 c serial interface) up to 9 db. the ana in pin is the analog input from the telephone chip set. it can be switched (by the serial bus) to the speaker output, the array input or to various other paths. this pin is designed to accept a nominal 1.11 vp-p when at its minimum gain (6 db) setting. see the ana in amplifier gain settings table on page 37. there is additional gain available in 3 db steps controlled from the i 2 c interface, if required, up to 15 db. aux in input amplifier aux in input c coup =0.1 rac coup 1 ana in input amplifier ana in input c coup = 0.1 rac coup 1
isd5100 series publication release date: may 16, 2007 - 29 - revision 1.4 7.4.2. isd5100 series analog structure (left half) description in put agc amp s um 1 2 (s1m1,s1m0) s ource mux sum 1 s um ming am p aux in amp fi lto s um1 mux an a in a m p ar ra y 2 (s1s1,s1s0) (ins0 ) 1514131211109876543210 aig1 aig0 aipd axg1 axg0 axpd ins0 aos2 aos 1aos0aopd ops 1 ops0 o pa1 opa 0 v lpd cfg0 1514131211109876543210 vls1 vl s0 v ol 2 vo l1 v ol 0 s1 s1 s 1s0s1m1s1m0 s 2 m 1 s2 m 0 fls0 fld 1 fld 0 f lpd ag pd cfg1 inp inso source 0 agc amp 1 aux in amp s1m 1 s1m0 source 0 0 both 0 1 sum1 mux only 1 0 inp only 1 1 power down s1s1 s1s0 sourc e 0 0 ana in 0 1 array 1 0 filto 1 1 n/c
isd5100 series - 30 - 7.4.3. isd5100 series aanalog structure (right half) description sum1 s um2 2 (s 2m1,s2m0) fi lter mux sum2 sum mi ng am p array 2 fi lto lo w pass filter in tern al clock mult ilevel s to ra g e array 1 (fls0) 1 (flpd) array ana in am p xclk (fld 1,fld0) 15141312111098 76 54 32 10 vls1 vls0 vo l2 v ol 1 vo l0 s1 s1 s1 s0 s1 m 1 s1 m 0 s2 m 1 s 2 m0 fls0 fld1 f ld0 fl pd agpd cfg1 fls 0 source 0 sum1 1 arra y flpd condition 0 power up 1 power down s2m1 s2m 0 source 0 0 both 0 1 ana in only 1 0 filto only 1 1 power down fld1 fld0 sample rate filter bandwidth 0 0 8 khz 3.6 khz 0 1 6.4 khz 2.9 khz 1 0 5.3 khz 2.4 khz 1 1 4.0 khz 1.8 khz filter mux filto
isd5100 series publication release date: may 16, 2007 - 31 - revision 1.4 7.4.4. volume control description vo l s um 2 vol mux s um 1 in p 2 an a in a m p vo lum e c ontrol (vls1,vls0) 3 (vol2,vol1 ,vol0 ) 1 (vlpd) vlpd condition 0 power up 1 power down vls1 vls0 source 0 0 ana in amp 0 1 sum2 1 0 sum1 1 1 inp vol2 vol1 vol 0 attenuation 0 0 0 0 db 0 0 1 4 db 0 1 0 8 db 0 1 1 12 db 1 0 0 16 db 1 0 1 20 db 1 1 0 24 db 1 1 1 28 db ins0 aig1 a ig 0 aip d a xg 1 a xg 0 ax pd a o s 2 aos1 aos0 aopd ops1 ops 0 o pa 1 o pa0 vlpd cfg0 1514131211109876543210 vl s1 vl s0 vo l 2vol1 s 1s1 s1s0s1m1s 1 m0 s2m1 s2m0 fls 0fld1fld0flpdagpd cfg1 vo l 0
isd5100 series - 32 - 7.4.5. speaker and aux out description s peaker sp+ sp? aux out car kit (1 vp -p ma x) ana in am p output mux filto s um 2 2 vo l (ops1,ops 0) 2 (opa1, opa0) ins0 1514131211109876543210 aig1 aig0 aipd axg1 axg0 axpd aos 2aos1aos0aopd ops1 ops 0 o pa 1 o pa0 vl pd cfg0 ops 1 ops 0 sourc e 0 0 vol 0 1 ana in 1 0 filto 1 1 sum2 opa1 opa0 spkr drive aux out 0 0 power down power down 0 1 3.6 v p-p @ 150 power down 1 0 23.5 mwatt @ 8 power down 1 1 power down 1 v p-p max @ 5 k
isd5100 series publication release date: may 16, 2007 - 33 - revision 1.4 7.4.6. ana out description chip set an a o u t + an a o u t ? *vol *filto *sum2 3 (ao s 2,aos1,aos 0) * fthru 1 (aopd) *inp *sum1 ( 1 vp - p m a x. f r om a ux in o r a rra y) (69 4 mvp-p ma x. fro m mi crop ho ne inp ut) ins 0 15141312111098 76 54 32 10 ai g1 aig0 aipd axg1 axg0 axpd ao s2 aos1 ao s0 ao pd ops1 ops0 opa1 opa0 vlpd cfg0 7.4.7. analog inputs microphone inputs the microphone inputs transfer the voice signal to the on-chip agc preamplifier or directly to the ana out mux, depending on the selected path. the direct path to the ana out mux has a gain of 6 db so a 208 mv p-p signal across the differential microphone inputs would give 416 mv p-p across the ana out pins. the agc circuit has a range of 45 db in order to deliver a nominal 694 mv p-p into the storage array from a typical electric microphone output of 2 to 20 mv p-p. the input impedance is typically 10k ? . the acap pin provides the capacitor connection for setting the parameters of the microphone agc circuit. it should have a 4.7 f capacitor connec ted to ground. it cannot be left floating. this is because the capacitor is also used in the playback mode for the automute circuit. this circuit reduces the amount of noise present in the output during quiet pauses. tying this pin to ground gives maximum gain; to vcca gives minimum gain for the agc amplifier but will cancel the automute function. aos2 aos1 aos 0 source 0 0 0 fthru 0 0 1 inp 0 1 0 vol 0 1 1 filto 1 0 0 sum1 1 0 1 sum2 1 1 0 n/c 1 1 1 n/c aopd condition 0 power up 1 power down *differential path
isd5100 series - 34 - mic + mic? ac ap fthru agc 1 (ag pd) 6 db to a u t o m u t e (pl ayb ac k o nly) * * differential path ag c 1514131211109876543210 vl s 1 vls0 vol2 vol1 vol0 s1s 1 s1s0 s1m1 s1 m0 s2m1 s2m0 fls0 fld1 fld0 flpd ag pd cfg1 ana in (analog input) the ana in pin is the analog input from the telephone chip set. it can be switched (by the i 2 c interface) to the speaker output, the array input or to various other paths. this pin is designed to accept a nominal 1.11 v p-p when at its minimum gain (6 db) setting. there is additional gain available, if required, in 3 db steps, up to 15 db. the gain settings are controlled from the i 2 c interface. ana in amplifier gain settings agp d condition 0 power up 1 power down mic in gain setting resistor ratio (rb/ra) gain gain 2 (db) 00 63.9 / 102 0.625 -4.1 01 77.9 / 88.1 0.883 -1.1 10 92.3 / 73.8 1.250 1.9 11 106 / 60 1.767 4.9 note: ra & rb are in k cfg0 setting (1) 0tlp input v p-p (3) aig1 aig0 gain (2) array in/out v p-p speaker out v p-p (4) 6 db 1.110 0 0 0.625 0.694 2.22 9 db 0.785 0 1 0.883 0.694 2.22 12 db 0.555 1 0 1.250 0.694 2.22 15 db 0.393 1 1 1.767 0.694 2.22 ana in input ana in input amplifier note: f cuttoff 2xr a c coup 1 r a r b c coup = 0.1 f internal to the device
isd5100 series publication release date: may 16, 2007 - 35 - revision 1.4 1. gain from ana in to sp+/- 2. gain from ana in to array in 3. 0tlp input is the reference transmission level point that is used for testing. this level is typically 3 db below clipping 4. speaker out gain set to 1.6 (high). (differential) aux in (auxiliary input) the aux in is an additional audio input to the isd5100-series, such as from the microphone circuit in a mobile phone ?car kit.? this input has a nominal 694 mv p-p level at its minimum gain setting (0 db). see the following table. additional gain is available in 3 db steps (controlled by the i 2 c interface) up to 9 db. aux in input modes aux in amplifier gain settings cfg0 setting (1) 0tlp input v p-p (3) axg1 axg0 gain (2) array in/out v p-p speaker out v p-p (4) 0 db 0.694 0 0 1.00 0.694 0.694 3 db 0.491 0 1 1.41 0.694 0.694 6 db 0.347 1 0 2.00 0.694 0.694 9 db 0.245 1 1 2.82 0.694 0.694 1. gain from aux in to ana out 2. gain from aux in to array in 3. 0tlp input is the reference transmission level poin t that is used for testing. this level is typically 3 db below clipping 4. differential gain setting resistor ratio (rb/ra) gain gain (2) (db) 00 40.1 / 40.1 1.0 0 01 47.0 / 33.2 1.414 3 10 53.5 / 26.7 2.0 6 11 59.2 / 21 2.82 9 note: ra & rb are in k aux in input ana in input amplifier note: f cuttoff 2xr a c coup 1 r a r b c coup = 0.1 f internal to the device
isd5100 series - 36 - 7.5. d igital m ode 7.5.1. erasing digital data the digital erase command can only erase an entire page at a time. this means that the d1 command only needs to include the 11-bit page address; the 5-bit for block address are left at 00000. once a page has been erased, each block may be written separately, 64 bits at a time. but, if a block has been previously written then the entire page of 2048 bits must be erased in order to re-write (or change) a block. a sequence might be look like: - read the entire page - store it in ram - change the desired bit(s) - erase the page - write the new data from ram to the entire page 7.5.2. writing digital data the digital write function allows the user to select a portion of the array to be used as digital memory. the partition between analog and digital memory is left up to the user. a page can only be either digital or analog, but not both. the minimum addressable block of memory in the digital mode is one block or 64 bits, when reading or writing. the address sent to the device is the 11-bit row (or page) address with the 5-bit scan (or block) address. however, one must send a digital erase before attempting to change digital data on a page. this means that even when changing only one of the 32 blocks, all 32 blocks will need to be rewritten to the page. command sequence: the chip enters digital mode by sending the enter digital mode command from power down. send the digital write @ addr command with the row address. after the address is entered, the data is sent in one-byte packets followed by an i 2 c acknowledge generated by the chip. data for each block is sent msb first. the data transfer is ended when the master generates an i 2 c stop condition. if only a partial block of data is sent before the stop condition, ?zero? is written in the remaining bytes; that is, they are left at the erase level. an erased page (row) will be read as all zeros. the device can buffer up to two blocks of data. if the device is unable to accept more data due to the internal write process, the scl line will be held low indicati ng to the master to halt data transfer. if the device encounters an overflow conditio n, it will respond by generating an interrupt condition and an i 2 c not acknowledge signal after the last valid byte of data. once data transfer is terminated, the device needs up to two cycles (64 us) to complete its internal write cycle before another command is sent. if an active command is sent before the internal cycle is finished, the part w ill hold scl low until the current command is finished. after writing is complete, send the exit digital mode command.
isd5100 series publication release date: may 16, 2007 - 37 - revision 1.4 7.5.3. reading digital data the digital read command utilizes the combined i 2 c command format. that is, a command is sent to the chip using the write data direction. then the data direction is reversed by sending a repeated start condition, and the slave address with r/w set to 1. after this, the slave device (isd5100- series) begins to send data to the master until the master generates a nack. if the part encounters an overflow condition, the int pin is pulled low. no other communication with the master is possible due to the master generating ack signals. digital write and digital read can be done a ?block? at a time. thus, only 64 bits need be read in each digital read command sequence. 7.5.4. example command sequences an explanation and graphical representation of the erase, write and read operations are found below. note: all sequences assumes that the chip is in power-down mode before the commands are sent. 7.5.4.1. erase digital data erase ===== i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - enter digital mode command waitack waitsclhigh i2cstop i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xd1) - digital erase command waitack waitsclhigh sendbyte(row/256) - high address byte
isd5100 series - 38 - waitack waitsclhigh sendbyte(row%256) - low address byte waitack waitsclhigh i2cstop repeat until the number of rac pulses are one less than the number of rows to delete { wait rac low wait rac high } note: if only one row is going to be erased, send the following stop command immediately after erase command and skip the loop above i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - stop digital erase waitack waitsclhigh i2cstop wait until erase of the last row has completed { wait rac low wait rac high } i2cstart sendbyte(0x80) - write, slave address zero waitack
isd5100 series publication release date: may 16, 2007 - 39 - revision 1.4 waitsclhigh sendbyte(0x40) - exit digital mode command waitack waitsclhigh i2cstop notes 1. erase operations must be addressed on a row boundary. the 5 lsb bits of the low address byte will be ignored. 2. i 2 c bus is released while erase proceeds. other devices may use the bus until it is time to execute the stop command that causes the end of the erase operation. 3. host processor must count rac cycles to determine where the chip is in the erase process, one row per rac cycle. rac pulses low for 0. 25 millisecond at the end of each erased row. the erase of the "next" row begins with the rising edge of rac. see the digital erase rac timing diagram on page 51. 4. when the erase of the last desired row begins, the following stop command (command byte = 80 hex) must be issued. this command must be completely given, including receiving the ack from the slave before the rac pin goes high at the end of the row.
isd5100 series - 40 - s slave address a w 40h a p s slave address a w con a p a s slave address w command byte d1 a data a data a high addr. byte low addr. byte p erase starts on falling edge of slave acknowledge note 2 a s s lave addre ss w command byte 80 "n" rac cycles n ote last erased row n ote a p
isd5100 series publication release date: may 16, 2007 - 41 - revision 1.4 suggested flow for digital erase in isd5100-series enter digital mode send erase command send stop command before rac wait for rac exit digital mode device powers down automatically yes no count rac for n-1 send stop command before next rac to erase multiple (n) pages (rows) yes no 6/20/2002 boj revision b wait for rac no yes rac\ signal 125 us 1.25 ms 80,c0 80,d1,nn,nn 80,c0 80,40 80,c0 stop command must be finished before rac\ rises 80 = powerup or stop c0 = enter digital mode d1 = erase digital page@ 40 = exit digital mode commands rac\ ~ 125 us rac\ ~ 125 us rac\ ~ 250 us 250 us
isd5100 series - 42 - 7.5.4.2. write digital data write ===== i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - enter digital mode command waitack waitsclhigh i2cstop i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc9) - write digital data command waitack waitsclhigh sendbyte(row/256) - high address byte waitack waitsclhigh sendbyte(row%256) - low address byte waitack waitsclhigh repeat until all data is sent { sendbyte(data) - send data byte waitack() waitsclhigh() } i2cstop
isd5100 series publication release date: may 16, 2007 - 43 - revision 1.4 i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0x40) - exit digital mode command waitack waitsclhigh i2cstop s slave address a w command b y te c9h a data a data a hi g h addr. b y te low addr. b y te ~ ~ data a data a ~ ~ data a p s slave address a w 40h a p s slave address a w con a p
isd5100 series - 44 - suggested flow for digital w rite in isd5100-series enter digital mode send write command w/ start address exit digital mode device pow ers dow n automatically yes 6/24/2002 boj revision n/c 80,c0 80,c9,nn,nn 80,40 80 = powerup or stop c0 = enter digital m ode c9 = w rite digital page@ 40 = exit digital mode commands byte counter =256? no w ait for scl high send data byte (send next byte)
isd5100 series publication release date: may 16, 2007 - 45 - revision 1.4 7.5.4.3. read digital data read ===== i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xc0) - enter digital mode waitack waitsclhigh i2cstop i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0xe1) - read digital data command waitack waitsclhigh sendbyte(row/256) - high address byte waitack waitsclhigh() sendbyte(row%256) - low address byte waitack waitsclhigh i2cstart - send repeat start command sendbyte(0x81) - read, slave address zero repeat until all data is read { data = readbyte() - se nd clocks to read data byte sendack - send nack on the last byte waitsclhigh - the only flow control available
isd5100 series - 46 - } i2cstop() i2cstart sendbyte(0x80) - write, slave address zero waitack waitsclhigh sendbyte(0x40) - exit digital mode waitack waitsclhigh i2cstop a s slave address w command b y te e1h a data a data a hi g h addr. b y te low addr. b y te s slave address a w 40h a p s slave address a w con a p data a data a ~ ~ ~ ~ p data n a s slave address r
isd5100 series publication release date: may 16, 2007 - 47 - revision 1.4 suggested flow for digital read in isd5100-series enter digital mode send read command w / start address exit dig ital mode device pow ers dow n automatically yes 6/24/2002 boj revision n/c 80,c0 80,e1,nn,nn 80,40 80 = powerup or stop c0 = enter digital mode e1 = read digital page@ 40 = exit digital m ode commands byte counter =256? no w ait for scl high read data byte (read next byte)
isd5100 series - 48 - 7.6. p in d etails 7.6.1. digital i/o pins scl (serial clock line) the serial clock line is a bi-directi onal clock line. it is an open-drain line requiring a pull-up resistor to vcc. it is driven by the "master" chips in a system and controls the timing of the data exchanged over the serial data line. sda (serial data line) the serial data line carries the data between devices on the i 2 c interface. data must be valid on this line when the scl is high. state changes can only take place when the scl is low. this is a bi-directional line requiring a pull-up resistor to vcc. rac (row address clock) rac is an open drain output pin that normally marks the end of a row. at the 8 khz sample frequency, the duration of this period is 256 ms. rac stays high for 248 ms and stays low for the remaining 8 ms before it reaches the end of a row. there are 2048 rows of memory in the isd5116 devices, 1024 rows in the isd5108, 512 rows in the isd5104 and 256 rows in the isd5102. 1 row rac waveform during 8 khz operation 256 msec t rac 8 msec t racl the rac pin remains high for 500 sec and stays low for 15.6 sec under the message cueing mode. see the timing parameters table on page 64 for rac timing information at other sample rates. when a record command is first initiated, the rac pin remains high for an extra t racml period, to load sample and hold circuits internal to the device. the rac pin can be used for message management techniques. 1 row rac waveform during message cueing @ 8khz operation 500 usec t racm 15.6 us t racml
isd5100 series publication release date: may 16, 2007 - 49 - revision 1.4 rac waveform during digital erase @ 8khz operation 1.25 ms trace .25 ms t racel int (interrupt) int is an open drain output pin. the isd5100 series interrupt pin goes low and stays low when an overflow (ovf) or end of message (eom) marker is detected. each operation that ends in an eom or ovf generates an interrupt, including the message cueing cycles. the interrupt is cleared by a read status instruction that will give a status byte out the sda line. xclk (external clock input) this is the external clock input. to use internal clock, this pin must be grounded (suggest connecting to v ssd ). while in internal clock mode, the isd5100 series are operated at one of four internal rates selected for its internal oscillator by the sample rate select bits. for precision timing control, external clock signal can be applied through this pin. in the external clock mode, the device can be clocked through the xclk pin at 4.096 mhz as described in section 7.4.3 on page 32. because the anti-aliasing and smoothing filters track the sample rate select bits, one must, for optimum performance, maintain the external clock at 4.096 mhz and set the sample rate configuration bits to one of the four values to properly set the filters to the correct cutoff frequency as described in section 7.4.3 on page 32. the duty cycle on the input clock is not critical, as the clock is immediately divided by two internally. external clock input table isd5116 duration (minutes) isd5108 duration (minutes) isd5104 duration (minutes) isd5102 duration (minutes) sample rate (khz) required clock (khz) fld1 fld0 filter knee (khz) 8.73 4.36 2.18 1.08 8.0 4096 0 0 3.4 10.9 5.45 2.72 1.35 6.4 4096 0 1 2.7 13.1 6.55 3.27 1.63 5.3 4096 1 0 2.3 17.5 8.75 4.37 2.18 4.0 4096 1 1 1.7
isd5100 series - 50 - a0, a1 (address pins) these two pins are normally strapped for the desir ed address that the isd5100 series will have on the i 2 c serial interface. if there are four of these devices on the bus, then each must be strapped differently in order to allow the master device to address them individually. the possible addresses range from 80h to 87h, depending upon whether the device is being written to, or read from, by the host. the isd5100 series have a 7-bit slave address of which only a0 and a1 are pin programmable. the eighth bit (lsb) is the r/w bit. thus, the address will be 1000 0xy0 or 1000 0xy1. (see the table in section 7.3.1 on page 13.) 7.6.2. analog i/o pins mic+, mic- (microphone input +/-) the microphone input transfers the voice signal to the on-chip agc preamplifier or directly to the ana out mux, depending on the selected path. the direct path to the ana out mux has a gain of 6 db so a 208 mv p-p signal across the differential microphone inputs would give 416 mv p-p across the ana out pins. the agc circuit has a range of 45 db in order to deliver a nominal 694 mv p-p into the storage array from a typical electret microphone output of 2 to 20 mv p-p. the input impedance is typically 10k ? . ana out+, ana out- (analog output +/-) this differential output is designed to go to the microphone input of the telephone chip set. it is de- signed to drive a minimum of 5 k ? between the ?+? and ??? pins to a nominal voltage level of 694 mv p-p. both pins have dc bias of approximately 1.2 vdc. the ac signal is superimposed upon this analog ground voltage. these pins can be used single-ended, getting only half the voltage. do not ground the unused pin. + internal to the device note: f cutoff = 2 rac coup 1 fthru c coup =0.1 f ra=10k 6db mic in 10k 0.1 1.5k electret microphone wm-54b panasonic 220 f 1.5k 1.5k agc mic+ mic-
isd5100 series publication release date: may 16, 2007 - 51 - revision 1.4 acap (agc capacitor) this pin provides the capacitor connection for setting the parameters of the microphone agc circuit. it should have a 4.7 f capacitor connected to ground. it cannot be left floating. this is because the capacitor is also used in the playback mode for the automute circuit. this circuit reduces the amount of noise present in the output during quiet pauses. tying this pin to ground gives maximum gain; tying it to v cca gives minimum gain for the agc amplifier but cancels the automute function. sp +, sp- (speaker +/-) this is the speaker differential output circuit. it is designed to drive an 8 ? speaker connected across the speaker pins up to a maximum of 23.5 mw rms power. this stage has two selectable gains, 1.32 and 1.6, which can be chosen through the configuration registers. these pins are biased to ap- proximately 1.2 vdc and, if used single-ended, must be capacitively coupled to their load. do not ground the unused pin. aux out (auxiliary output) the aux out is an additional audio output pin to be used, for example, to drive the speaker circuit in a ?car kit.? it drives a minimum load of 5k ? and up to a maximum of 1v p-p. the ac signal is superimposed on approximately 1.2 vdc bias and must be capacitively coupled to the load. speaker sp + sp ? aux out car kit (1 vp -p max) an a in amp output mux filto sum 2 2 vo l (ops1,ops0) 2 (opa1, opa0) ins0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ai g1 ai g0 ai pd axg 1 axg0 axpd ao s2 ao s1 aos0 ao pd ops1 ops0 opa1 opa0 vlpd cfg0 ops1 ops0 source 0 0 vol 0 1 ana in 1 0 filto 1 1 sum2 opa1 opa0 spkr drive aux out 0 0 power down power down 0 1 3.6 v p.p @150 power down 1 0 23.5 mwatt @ 8 power down 1 1 power down 1 v p.p max @ 5k
isd5100 series - 52 - ana in (analog input) the ana in pin is the analog input from the telephone chip set. it can be switched (by the i 2 c interface) to the speaker output, the array input or to various other paths. this pin is designed to accept a nominal 1.11 v p-p when at its minimum gain (6 db) setting. there is additional gain available, if required, in 3 db steps, up to 15 db. the gain settings are controlled from the i 2 c interface. ana in input modes ana in amplifier gain settings cfg0 setting (1) 0tlp input v p-p (3) aig1 aig0 gain (2) array in/out v p-p speaker out v p-p (4) 6 db 1.110 0 0 0.625 0.694 2.22 9 db 0.785 0 1 0.883 0.694 2.22 12 db 0.555 1 0 1.250 0.694 2.22 15 db 0.393 1 1 1.767 0.694 2.22 1. gain from ana in to sp+/- 2. gain from ana in to array in 3. 0tlp input is the reference transmission level point that is used for testing. this level is typically 3 db below clipping 4. speaker out gain set to 1.6 (high). (differential) gain setting resistor ration (rb/ra) gain gain 2 (db) 00 63.9 / 102 0.625 -4.1 01 77.9 / 88.1 0.88 -1.1 10 92.3 / 73.8 1.25 1.9 11 106 / 60 1.77 4.9 note: ra & rb are in k ana in input ana in input amplifier note: f cuttoff 2xr a c ccup 1 r a r b c coup = 0.1 f internal to the device
isd5100 series publication release date: may 16, 2007 - 53 - revision 1.4 aux in (auxiliary input) the aux in is an additional audio input to the isd5100-series, such as from the microphone circuit in a mobile phone ?car kit.? this input has a nominal 694 mv p-p level at its minimum gain setting (0 db). see the aux in amplifier gain settings table on page 56. additional gain is available in 3 db steps (controlled by the i 2 c interface) up to 9 db. aux in input modes aux in amplifier gain settings cfg0 setting (1) 0tlp input v p-p (3) axg1 axg0 gain (2) array in/out v p-p speaker out v p-p (4) 0 db 0.694 0 0 1.00 0.694 0.694 3 db 0.491 0 1 1.41 0.694 0.694 6 db 0.347 1 0 2.00 0.694 0.694 9 db 0.245 1 1 2.82 0.694 0.694 1. gain from aux in to ana out 2. gain from aux in to array in 3. 0tlp input is the reference transmission level point that is used for testing. this level is typically 3 db below clipping 4. differential gain setting resistor ratio (rb/ra) gain gain (2) (db) 00 40.1 / 40.1 1.0 0 01 47.0 / 33.2 1.414 3 10 53.5 / 26.7 2.0 6 11 59.2 / 21 2.82 9 note: ra & rb are in k aux in input ana in input amplifier note: f cuttoff 2xr a c ccup 1 r a r b c coup = 0.1 f internal to the device
isd5100 series - 54 - 7.6.3. power and ground pins v cca , v ccd (voltage inputs) to minimize noise, the analog and digital circuits in the isd5100 series devices use separate power busses. these +3 v busses lead to separate pins. tie the v ccd pins together as close as possible and decouple both supplies as near to the package as possible. v ssa , v ssd (ground inputs) the isd5100 series utilizes separate analog an d digital ground busses. the analog ground (v ssa ) pins should be tied together as close to the package as possible and connected through a low- impedance path to power supply ground. the digital ground (v ssd ) pin should be connected through a separate low impedance path to power supply ground. these ground paths should be large enough to ensure that the impedance between the v ssa pins and the v ssd pin is less than 3 ? . the backside of the die is connected to v ssd through the substrate resistance. in a chip-on-board design, the die attach area must be connected to v ssd . nc (not connect) these pins should not be connected to the board at any time. connection of these pins to any signal, ground or v cc, may result in incorrect device behavior or cause damage to the device.
isd5100 series publication release date: may 16, 2007 - 55 - revision 1.4 7.6.4. pcb layout examples for soic package : pc board traces and the three chip capacitors are on the bottom side of the board. o o o o o o o o o o o o o o o o o o o o o o o o o o o o v c c d xclk analog ground 1 v ssa to v cca v s s d (digital ground) note 1: v ssd traces should be kept separated back to the v ss supply feed point.. note 2: v ccd traces should be kept separate back to the v cc supply feed point. note 3: the digital and analog grounds tie together at the power supply. the v cca and v ccd supplies will also need filter capacitors per good engineering practice (typ. 50 to 100 uf). c1 c2 c3 note 1 note 2 c1=c2=c3=0.1 uf chip capacitors note 3 note 3 for tsop package : notes: [1] v ssd traces should be kept separated back to the v ss supply feedpoint. [2] v ccd traces should be kept separate back to the v cc supply feedpoint. [3] digital and analog grounds tie together at power supply. the v cca and v ccd supplies will also need filter capacitors per good engineering practice (typ. 50 to 100 uf). v cca v ssa v ssd v ccd note [2] note [1] note [3] v ccd v ccd v ssd v ssd v ssa v cca v ssa 1 v ssa
isd5100 series - 56 - 8.timing diagrams 8.1. i 2 c t iming d iagram t low t sclk t high t f t r t su-dat t su-sto t f start sda scl stop
isd5100 series publication release date: may 16, 2007 - 57 - revision 1.4 i 2 c interface timing standard-mode fast-mode parameter symbol min. max. min. max. unit scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd-sta 4.0 - 0.6 - s low period of the scl clock t low 4.7 - 1.3 - s high period of the scl clock t high 4.0 - 0.6 - s set-up time for a repeated start condition t su-sta 4.7 - 0.6 - s data set-up time t su-dat 250 - 100 (1) - ns rise time of both sda and scl signals t r - 1000 20 + 0.1c b (2) 300 ns fall time of both sda and scl signals t f - 300 20 + 0.1c b (2) 300 ns set-up time for stop condition t su-sto 4.0 - 0.6 - s bus-free time between a stop and start condition t buf 4.7 - 1.3 - s capacitive load for each bus line c b - 400 - 400 pf noise margin at the low level for each connected device (including hysteresis) v nl 0.1 v dd - 0.1 v dd - v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 v dd - 0.2 v dd - v 1. a fast-mode i 2 c-interface device can be used in a standard-mode i 2 c-interface system, but the requirement t su;dat > 250 ns must then be met. this will automati cally be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the sc l signal, it must output t he next data bit to the sda line; t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c -interface specification) before the scl line is released. 2. c b = total capacitance of one bus line in pf. if mixed with hs mode devices, faster fall-times are allowed.
isd5100 series - 58 - 8.2. p layback and s top c ycle sda scl ana in ana out data clock pulses stop play at addr t stop t start stop
isd5100 series publication release date: may 16, 2007 - 59 - revision 1.4 8.3. e xample of p ower u p c ommand ( first 12 bits )
isd5100 series - 60 - 9. absolute maximum ratings absolute maximum ratings (packaged parts) (1) condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c voltage applied to any pins (v ss - 0.3v) to (v cc + 0.3v) voltage applied to any pin (input current limited to +/-20 ma) (v ss ? 1.0v) to (v cc + 1.0v) lead temperature (soldering ? 10 seconds) 300 0 c v cc - v ss -0.3v to +5.5v 1. stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functi onal operation is not impl ied at these conditions. absolute maximum ratings (die) (1) condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c voltage applied to any pads (v ss - 0.3v) to (v cc + 0.3v) v cc - v ss -0.3v to +5.5v 1. stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functi onal operation is not implied at these conditions.
isd5100 series publication release date: may 16, 2007 - 61 - revision 1.4 operating conditions (packaged parts) conditions values commercial operating temperature [1] 0 c to +70 c supply voltage (v cc ) [2] +2.7v to +3.3v ground voltage (v ss ) [3] 0v voltage applied to any pins (v ss - 0.3v) to (v cc + 0.3v) conditions values industrial operating temperature [1] -40 c to +85 c isd5102, isd5104, isd5 116 +2.7v to +3.3v supply voltage (v cc ) [2] isd5108 +2.7v to +3.6v ground voltage (v ss ) [3] 0v voltage applied to any pins (v ss - 0.3v) to (v cc + 0.3v) operating conditions (die) conditions values die operating temperature range [1] 0 c to +50 c supply voltage (v cc ) [2] +2.7v to +3.3v ground voltage (v ss ) [3] 0v voltage applied to any pads (v ss - 0.3v) to (v cc + 0.3v) [1] case temperature [2] v cc = v cca = v ccd [3] v ss = v ssa = v ssd
isd5100 series - 62 - 10. electrical characteristics 10.1. g eneral p arameters symbol parameters min (2) typ (1) max (2) unit s conditions v il input low voltage v cc x 0.2 v v ih input high voltage v cc x 0.8 v v ol scl, sda output low voltage 0.4 v i ol = 3 a v il2v input low voltage for 2v interface 0.4 v apply only to scl, sda v ih2v input high voltage for 2v interface 1.6 v apply only to scl, sda v ol1 rac, int output low voltage 0.4 v i ol = 1 ma v oh output high voltage v cc ? 0.4 v i ol = -10 a i cc v cc current (operating) - playback - record - feedthrough 15 30 12 25 40 15 ma ma ma no load (3) no load (3) no load (3) i sb v cc current (standby) 1 10 a [3] i il input leakage current 1 a [1] typical values: t a = 25c and vcc = 3.0 v. [2] all min/max limits are guaranteed by winbond via electric al testing or characterization. not all specifications are 100 percent tested. [3] all v cc and v ss are connected appropriately and others are floated.
isd5100 series publication release date: may 16, 2007 - 63 - revision 1.4 10.2. t iming p arameters symbol parameters min (2) typ (1) max (2) units conditions f s sampling frequency 8.0 6.4 5.3 4.0 khz khz khz khz (5) (5) (5) (5) f cf filter knee 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 3.4 2.7 2.3 1.7 khz khz khz khz knee point (3)(7) knee point (3)(7) knee point (3)(7) knee point (3)(7) isd5116 isd5108 isd5104 isd5102 t rec record duration 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 8.73 10.9 13.1 17.5 4.36 5.45 6.55 8.75 2.18 2.72 3.27 4.37 1.08 1.35 1.63 2.18 min min min min (6) (6) (6) (6) isd5116 isd5108 isd5104 isd5102 t play playback duration 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 8.73 10.9 13.1 17.5 4.36 5.45 6.55 8.75 2.18 2.72 3.27 4.37 1.08 1.35 1.63 2.18 min min min min (6) (6) (6) (6) t pud power-up delay 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 1 1 1 1 msec msec msec msec t stop/ pause stop or pause record or play 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 32 40 48 64 msec msec msec msec t rac rac clock period 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 256 320 384 msec msec msec (9) (9) (9)
isd5100 series - 64 - 4.0 khz (sample rate) 512 msec (9) t racl rac clock low time 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 8 10 12.1 16 msec msec msec msec t racm rac clock period in message cueing mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 500 625 750 1000 sec sec sec sec t racml rac clock low time in message cueing mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 15.6 19.5 23.4 31.2 sec sec sec sec t race rac clock period in digital erase mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 1.25 1.56 1.87 2.50 msec msec msec msec t racel rac clock low time in digital erase mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 0.25 0.31 0.37 0.50 msec msec msec msec thd total harmonic distortion ana in to array, array to spkr 1 1 2 2 % % @1 khz at 0tlp, sample rate = 5.3 khz
isd5100 series publication release date: may 16, 2007 - 65 - revision 1.4 10.3. a nalog p arameters microphone input (14) symbol parameters min (2) typ (1)(14) max (2) units conditions v mic+/- mic +/- input voltage 300 mv peak-to-peak (4)(8) v mic (0tlp) mic +/- input reference transmission level point (0tlp) 208 mv peak-to-peak (4)(10) a mic gain from mic +/- input to ana out 5.5 6.0 6.5 db 1 khz at v mic (0tlp) (4) a mic (gt) mic +/- gain tracking +/-0.1 db 1 khz, +3 to ?40 db 0tlp input r mic microphone input resistance 10 k mic- and mic+ pins a agc microphone agc amplifier range 6 40 db over 3-300 mv range ana in (14) symbol parameters min (2) typ (1)(14) max (2) units conditions v ana in ana in input voltage 1.6 v peak-to-peak (6 db gain setting) v ana in (0tlp) ana in (0tlp) input voltage 1.1 v peak-to-peak (6 db gain setting) (10) a ana in (sp) gain from ana in to sp+/- +6 to +15 db 4 steps of 3 db a ana in (aux out) gain from ana in to aux out -4 to +5 db 4 steps of 3 db a ana in (ga) ana in gain accuracy -0.5 +0.5 db (11) a ana in (gt) ana in gain tracking +/-0.1 db 1000 hz, +3 to ?45 db 0tlp input, 6 db setting r ana in ana in input resistance (6 db to +15 db) 10 to 100 k depending on ana in gain
isd5100 series - 66 - aux in (14) symbol parameters min (2) typ (1)(14) max (2) units conditions v aux in aux in input voltage 1.0 v peak-to-peak (0 db gain setting) v aux in (0tlp) aux in (0tlp) input voltage 694.2 mv peak-to-peak (0 db gain setting) a aux in (ana out) gain from aux in to ana out 0 to +9 db 4 steps of 3 db a aux in (ga) aux in gain accuracy -0.5 +0.5 db (11) a aux in (gt) aux in gain tracking +/-0.1 db 1000 hz, +3 to ?45 db 0tlp input, 0 db setting r aux in aux in input resistance 10 to 100 k depending on aux in gain speaker outputs (14) symbol parameters min (2) typ (1)(14) max (2) units conditions v sphg sp+/- output voltage (high gain setting) 3.6 v peak-to-peak, differential load = 150 , opa1, opa0 = 01 r splg sp+/- output load imp. (low gain) 8 opa1, opa0 = 10 r sphg sp+/- output load imp. (high gain) 70 150 opa1, opa0 = 01 c sp sp+/- output load cap. 100 pf v spag sp+/- output bias voltage (analog ground) 1.2 vdc v spdco speaker output dc offset +/-100 mv dc with ana in to speaker, ana in ac coupled to v ssa icn ana in/(sp+/-) ana in to sp+/- idle channel noise -65 db speaker load = 150 (12)(13) c r t (sp+/-)/ana out sp+/- to ana out cross talk -65 db 1 khz 0tlp input to ana in, with mic+/- and aux in ac coupled to v ss , and measured at ana out feed through mode (12) psrr power supply rejection ratio -55 db measured with a 1 khz, 100 mv p-p sine wave input at
isd5100 series publication release date: may 16, 2007 - 67 - revision 1.4 v cc and v cc pins f r frequency response (300- 3400 hz) + 0.5 db with 0tlp input to ana in, 6 db setting (12) guaranteed by design p outlg power output (low gain setting) 23.5 mw rms differential load at 8 sinad sinad ana in to sp+/- 62.5 db 0tlp ana in input minimum gain, 150 load (12)(13) ana out (14) symbol parameters min (2) type (1)(14) max (2) units conditions sinad sinad, mic in to ana out 62.5 db load = 5k (12)(13) sinad sinad, aux in to ana out (0 to 9 db) 62.5 db load = 5k (12)(13) ico nic/ana out idle channel noise ? microphone -65 db load = 5k (12)(13) icn aux in/ana out idle channel noise ? aux in (0 to 9 db) -65 db load = 5k (12)(13) psrr (ana out) power supply rejection ratio -40 db measured with a 1 khz, 100 mv p-p sine wave to v cca , v ccd pins v bias ana out+ and ana out- 1.2 vdc inputs ac coupled to v ssa v offset ana out+ to ana out- +/- 100 mv dc inputs ac coupled to v ssa r l minimum load impedance 5 k differential load f r frequency response (300- 3400 hz) + 0.5 db 0tlp input to mic+/- in feedthrough mode. 0tlp input to aux in in feedthrough mode (12) c r t ana out/(sp+/-) ana out to sp+/- cross talk -65 db 1 khz 0tlp output from ana out, with ana in ac coupled to v ssa , and measured at sp+/- (12)
isd5100 series - 68 - c r t ana out/aux out ana out to aux out cross talk -65 db 1 khz 0tlp output from ana out, with ana in ac coupled to v ssa , and measured at aux out (12) aux out (14) symbol parameters min (2) typ (1(14)) max (2) units conditions v aux out aux out ? maximum output swing 1.0 v 5k load r l minimum load impedance 5 k c l maximum load capacitance 100 pf v bias aux out 1.2 vdc sinad sinad ? ana in to aux out 62.5 db 0tlp ana in input, minimum gain, 5k load (12)(13) icn (aux out) idle channel noise ? ana in to aux out -65 db load=5k (12)(13) c r t aux out/ana out aux out to ana out cross talk -65 db 1 khz 0tlp input to ana in, with mic +/- and aux in ac coupled to v ssa , measured at sp+/-, load = 5k . referenced to nominal 0tlp @ output volume control (14) symbol parameters min (2) typ (1)(14) max (2) units conditions a out output gain -28 to 0 db 8 steps of 4 db, referenced to output tolerance for each step -1.0 +1.0 db ana in 1.0 khz 0tlp, 6 db gain setting measured differentially at sp+/-
isd5100 series publication release date: may 16, 2007 - 69 - revision 1.4 conditions 1. typical values: t a = 25c and vcc = 3.0v. 2. all min/max limits are guaranteed by winbond vi a electrical testing or characterization. not all specifications are 100 percent tested. 3. low-frequency cut off depends upon the value of external capacitors (see pin descriptions). 4. differential input mode. nominal diffe rential input is 208 mv p-p. (0tlp) 5. sampling frequency can vary as much as ?6/+4 percent over the industria l temperature and voltage ranges. for greater stability, an external cl ock can be utilized (see pin descriptions). 6. playback and record duration can vary as much as ?6/+4 percent over the industrial temperature and voltage ranges. for greater stability, an external clock can be utilized (see pin descriptions). 7. filter specification applies to the low pass filter. 8. for optimal signal quality, th is maximum limit is recommended. 9. when a record command is sent, t rac = t rac + t racl on the first page addressed. 10. the maximum signal level at any input is defined as 3.17 db higher than the reference transmission level point. (0tlp) this is the po int where signal clipping may begin. 11. measured at 0tlp point for each gain setting. see the ana in table and aux in table on pages 54 and 55 respectively. 12. 0tlp is the reference test level through inputs and outputs. see the ana in table and aux in table on pages 54 and 55 respectively. 13. referenced to 0tlp input at 1 khz, measured over 300 to 3,400 hz bandwidth. 14. for die, only typical values are applicable. 10.4. c haracteristics of t he i 2 c s erial i nterface the i 2 c interface is for bi-directional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the interface bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse, as change s in the data line at this time will be interpreted as a control signal.
isd5100 series - 70 - start and stop conditions both data and clock lines remain high when the interface bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). system configuration a device generating a message is a ?transmitter?; a device receiving a message is the ?receiver?. th system configuration a device generating a message is a ?transmitter?; a device receiving a message is the ?receiver?. the device that controls the message i sthe ?master? and the devices that are controlled by the master are the ?slaves?. sda scl s p start condition stop condition definition of start and stop conditions sda scl sda scl data line stable; data v a li d changed of data a ll o w ed bit transfer on the i 2 c-bus
isd5100 series publication release date: may 16, 2007 - 71 - revision 1.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the interface bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. in addition, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse so that the sda line is stable low during the high period of the acknowledge related clock pulse (set- up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. example of an i 2 c-bus confi g uration usin g two microcontrollers sda scl micro- controller lcd driver static ram or eeprom gate array isd 5116 8 data output by transmitter data output by receiver scl from master not acknowledge acknowledge dock pulse for acknowledgement s start condition acknowledge on the i 2 c-bus 1 2 9
isd5100 series - 72 - 10.5. i 2 c p rotocol since the i2c protocol allows multiple devices on the bus, each device must have an address. this address is known as a ?slave address?. a slave address consists of 7 bits, followed by a single bit that indicates the direction of data flow. this single bit is 1 for a write cycle, which indicates the data is being sent from the current bus master to the device being addressed. this single bit is a 0 for a read cycle, which indicates that the data is being sent from the device being addressed to the current bus master. for example, the valid slave addresses for the isd5100 series device, for both write and read cycles, are shown in section 7.3.1 on page 13 of this datasheet. before any data is transmitted on the i2c interface, the current bus master mu st address the slave it wishes to transfer data to or from. the slave address is always sent out as the 1 st byte following the start condition sequence. an example of a master tr ansmitting an address to a isd5100 series slave is shown below. in this case, the master is writing data to the slave and the r/w bit is ?0?, i.e. a write cycle. all the bits transferred are from the master to the slave, except for the indicated acknowledge bits. the following example details the transfer explained in section 7.3.1 - 2 - 3 on pages 13-20 of this datasheet . master transmits to slave receiver (write) mode swaaaap slave address command byte high addr. byte low addr. byte acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w start bit stop bit a common procedure in the isd5100 series is the reading of the status bytes. the read status condition in the isd5100 series is triggered when the master addresses the chip with its proper slave address, immediately followed by the r/w bit set to a ?1? and without the command byte being sent. this is an example of the master sending to the slave, immediately followed by the slave sending data back to the master. the ?n? not-acknowledge cycle from the master ends the transfer of data from the slave. the following example details the transfer explained in section 7.3.1 on page 13 of this datasheet.
isd5100 series publication release date: may 16, 2007 - 73 - revision 1.4 master reads from slave immediately after first byte (read mode) r/w from master start bit from master stop bit from master acknowledgement from slave acknowledgement from master not-acknowledged from master acknowledgement from master from master from slave from slave from slave sra a a n p low addr byte slave address status word high addr. byte another common operation in the isd5100 series is the reading of digital data from the chip?s memory array at a specific address. this requires the i 2 c interface master to first send an address to the isd5100 series slave device, and then receive data from the slave in a single i 2 c operation. to accomplish this, the data direction r/w bit must be changed in the middle of the command. the following example shows the master sending the slave address, then sending a command byte and 2 bytes of address data to the isd5100-series, and then immediately changing the data direction and reading some number of bytes from the chip?s digital array. an unlimited number of bytes can be read in this operation. the ?n? not-acknowledge cycle from the master forces the end of the data transfer from the slave. the following example details the transfer explained in section 7.5.4 on page 47 of this datasheet. master reads from the slave after setting data address in slave (write data address, read data) swa a a a slave address command byte high addr. byte low addr. byte acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w from master start bit from master sra a a n p 8 bits of data slave address 8 bits of data 8 bits of data r/w from master start bit from master stop bit from master acknowledgement from slave acknowledgement from master not-acknowled from master acknowledgement from master from master from slave from slave from slave
isd5100 series - 74 - 11. typical application circuit the following typical application example on isd5100 series is for references only. they make no representation or warranty that such applications shall be suitable for the use specified. it?s customer?s obligation to verify the design in its own system for the functionalities, voice quality, current consumption, and etc. in addition, the below notes apply to the following application examples: * the suggested values are for references only. depending on system requirements, they can be adjusted for functionalities and better performance. it is important to have a separate path for each ground and power back to the related terminals to minimize the noise. besides, the power supplies should be decoupled as close to the device as possible. also, it is crucial to follow good audio design practices in layout and power supply decoupling. see recommendations in applicatio n notes from our websites. example #1: recording via microphone scl sda a1 a0 mic+ mic- acap sp+ sp- 5100 1 2 3 4 16 14 to c i 2 c interface & address setting soic / pdip 8 10 13 v cc 220 f* electret microphone c i/o xclk ana in aux in ana out+ ana out- aux out 26 18 19 11 12 20 v ccd v ccd v ssd v ssd 27 28 5 6 v cc 0.1 f rac int 24 25 to c i/o for message management (optional) v ssa v ssa v ssa 9 15 23 v cca 17 0.1 f 1.5k * ? 1.5k * ? 1.5k * ? 0.1 f* 0.1 f* 4.7 f*
isd5100 series publication release date: may 16, 2007 - 75 - revision 1.4 12. package specification 12.1. 28-l ead 8 x 13.4 mm p lastic t hin s mall o utline p ackage (tsop) t ype 1 - iqc a a a 2 1 l l 1 y e h d d b e c min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 11.70 7.90 13.20 0.50 0.00 0 0.20 0.27 0.15 0.21 11.80 11.90 8.00 8.10 13.40 13.60 0.55 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.008 0.011 0.004 0.006 0.008 0.461 0.465 0.469 0.311 0.315 0.319 0.520 0.528 0.536 0.022 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm
isd5100 series - 76 - 12.2. 28-l ead 8 x 13.4 mm p lastic t hin s mall o utline p ackage (tsop) t ype 1 min nom max min nom max a 0.520 0.528 0.535 13.20 13.40 13.60 b 0.461 0.465 0.469 11.70 11.80 11.90 c 0.311 0.315 0.319 7.90 8.00 8.10 d 0.002 0.006 0.05 0.15 e 0.007 0.009 0.011 0.17 0.22 0.27 f 0.0217 0.55 g 0.037 0.039 0.041 0.95 1.00 1.05 h 0 0 3 0 6 0 0 0 3 0 6 0 i 0.020 0.022 0.028 0.50 0.55 0.70 j 0.004 0.008 0.10 0.21 note: lead coplanarity to be within 0.004 inches. inches millimeters plastic thin small outline package (tsop) type 1 dimensions 5 6 7 8 9 10 11 12 13 14 2 3 4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a b g f c d e h j i a b g c f e h j 4 8 10 1 2 3 5 6 7 9 11 12 13 14 18 20 24 17 16 15 19 21 22 23 25 26 27 28
isd5100 series publication release date: may 16, 2007 - 77 - revision 1.4 12.3. 28-l ead 300-m il p lastic s mall o utline i ntegrated c ircuit (soic) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 45 67 8 910 11 12 13 14 a d e f b g c h min nom max min nom max a 0.701 0.706 0.711 17.81 17.93 18.06 b 0.097 0.101 0.104 2.46 2.56 2.64 c 0.292 0.296 0.299 7.42 7.52 7.59 d 0.005 0.009 0.0115 0.127 0.22 0.29 e 0.014 0.016 0.019 0.35 0.41 0.48 f 0.050 1.27 g 0.400 0.406 0.410 10.16 10.31 10.41 h 0.024 0.032 0.040 0.61 0.81 1.02 note: lead coplanarity to be within 0.004 inches. plastic small outline integrated circuit (soic) dimensions inches millimeters
isd5100 series - 78 - 12.4. 28-l ead 600-m il p lastic d ual i nline p ackage (pdip) plastic dual inline package (pdip) (p) dimensions inches millimeters min nom max min nom max a 1.445 1.450 1.455 36.70 36.83 36.96 b1 0.150 3.81 b2 0.065 0.070 0.075 1.65 1.78 1.91 c1 0.600 0.625 15.24 15.88 c2 0.530 0.540 0.550 13.46 13.72 13.97 d 0.19 4.83 d1 0.015 0.38 e 0.125 0.135 3.18 3.43 f 0.015 0.018 0.022 0.38 0.46 0.56 g 0.055 0.060 0.065 1.40 1.52 1.65 h 0.100 2.54 j 0.008 0.010 0.012 0.20 0.25 0.30 s 0.070 0.075 0.080 1.78 1.91 2.03 0 0 15 0 15
isd5100 series publication release date: may 16, 2007 - 79 - revision 1.4 12.5 isd5116 d ie i nformation isd5116 v ssa mic + mic - ana out + ana out - acap sp - v ssa [2] sp + v cca [2] ana in aux in aux out v ssd v ssd a0 sda a1 scl v ccd xclk rac v ssa int v ccd isd5116 device die dimensions x: 4125 i y: 8030 i die thickness [3] 292.1 i ? 12.7 i pad opening single pad: 90 x 90 i double pad: 180 x 90 i notes 1. the backside of die is internally connected to vss. it must not be connected to any other potential or damage may occur. 2. double bond recommended, if tr eated as single doubled-pad. 3. this figure reflects the current die thickness. pl ease contact winbond as this thickness may change in the future.
isd5100 series - 80 - isd5116 pad coordinates (with respect to die center in m) pad pad name x axis y axis v ssa analog ground 1879.45 3848.65 rac row address clock 1536.20 3848.65 int interrupt 787.40 3848.65 xclk external clock input 475.60 3848.65 v ccd digital supply voltage 288.60 3848.65 v ccd digital supply voltage 73.20 3848.65 scl serial clock line -201.40 3848.65 a1 address 1 -560.90 3848.65 sda serial data address -818.20 3848.65 a0 address 0 -1369.40 3848.65 v ssd digital ground -1671.30 3848.65 v ssd digital ground -1842.90 3848.65 v ssa analog ground -1948.00 -3841.60 mic+ non-inverting microphone input -1742.20 -3841.60 mic- inverting microphone input -1509.70 -3841.60 ana out+ non-inverting analog output -1248.00 -3841.60 ana out- inverting analog output -913.80 -3841.60 acap agc/automute cap -626.50 -3841.60 sp- speaker negative -130.70 -3841.60 v ssa analog ground 202.90 -3841.60 v ssa analog ground 292.90 -3841.60 sp+ speaker positive 626.50 -3841.60 v cca analog supply voltage 960.10 -3841.60 v cca analog supply voltage 1050.10 -3841.60 ana in analog input 1257.40 -3841.60 aux in auxiliary input 1523.00 -3841.60 aux out auxiliary output 1767.20 -3841.60
isd5100 series publication release date: may 16, 2007 - 81 - revision 1.4 12.6 isd5108 d ie i nformation isd5108 v ssa mic + mic - ana out + ana out - acap sp - v ssa [2] sp + v cca [2] ana in aux in aux out v ssd v ssd a0 sda a1 scl v ccd xclk rac v ssa int v ccd isd5108 device die dimensions (include scribe line) x: 4230 i y: 6090 i die thickness [3] 292.1 i ? 12.7 i pad opening single pad: 90 x 90 i double pad: 180 x 90 i notes 1. the backside of die is internally connected to vss. it must not be connected to any other potential or damage may occur. 2. double bond recommended, if tr eated as single doubled-pad. 3. this figure reflects the current die thickness. pl ease contact winbond as this thickness may change in the future.
isd5100 series - 82 - isd5108 pad coordinates (with respect to die center in m) pad pad name x axis y axis v ssa analog ground 1882.40 2820.65 rac row address clock 1539.15 2820.65 int interrupt 790.35 2820.65 xclk external clock input 478.55 2820.65 v ccd digital supply voltage 291.55 2820.65 v ccd digital supply voltage 76.15 2820.65 scl serial clock line -198.45 2820.65 a1 address 1 -557.95 2820.65 sda serial data address -815.25 2820.65 a0 address 0 -1366.45 2820.65 v ssd digital ground -1668.35 2820.65 v ssd digital ground -1839.95 2820.65 v ssa analog ground -1945.05 -2821.60 mic+ non-inverting microphone input -1739.25 -2821.60 mic- inverting microphone input -1506.75 -2821.60 ana out+ non-inverting analog output -1245.05 -2821.60 ana out- inverting analog output -910.85 -2821.60 acap agc/automute cap -623.55 -2821.60 sp- speaker negative -127.75 -2821.60 v ssa analog ground 205.85 -2821.60 v ssa analog ground 295.85 -2821.60 sp+ speaker positive 629.45 -2821.60 v cca analog supply voltage 963.05 -2821.60 v cca analog supply voltage 1053.05 -2821.60 ana in analog input 1260.35 -2821.60 aux in auxiliary input 1525.95 -2821.60 aux out auxiliary output 1770.15 -2821.60
isd5100 series publication release date: may 16, 2007 - 83 - revision 1.4 12.7 isd5104 d ie i nformation isd5104 v ssa mic + mic - ana out + ana out - acap sp - v ssa [2] sp + v cca [2] ana in aux in aux out v ssd v ssd a0 sda a1 scl v ccd xclk rac v ssa int v ccd isd5104 device die dimensions (include scribe line) x: 4230 i y: 5046 i die thickness [3] 292.1 i ? 12.7 i pad opening single pad: 90 x 90 i double pad: 180 x 90 i notes 1. the backside of die is internally connected to vss. it must not be connected to any other potential or damage may occur. 2. double bond recommended, if tr eated as single doubled-pad. 3. this figure reflects the current die thickness. pl ease contact winbond as this thickness may change in the future.
isd5100 series - 84 - isd5104 pad coordinates (with respect to die center in m) pad pad name x axis y axis v ssa analog ground 1882.4 2306.65 rac row address clock 1539.15 2306.65 int interrupt 790.35 2306.65 xclk external clock input 478.55 2306.65 v ccd digital supply voltage 291.55 2306.65 v ccd digital supply voltage 76.15 2306.65 scl serial clock line -198.45 2306.65 a1 address 1 -557.95 2306.65 sda serial data address -815.25 2306.65 a0 address 0 -1366.45 2306.65 v ssd digital ground -1839.95 2306.65 v ssd digital ground -1668.35 2306.65 v ssa analog ground -1945.05 -2311.60 mic+ non-inverting microphone input -1739.25 -2311.60 mic- inverting microphone input -1506.75 -2311.60 ana out+ non-inverting analog output -1245.05 -2311.60 ana out- inverting analog output -910.85 -2311.60 acap agc/automute cap -623.55 -2311.60 sp- speaker negative -127.75 -2311.60 v ssa analog ground 205.85 -2311.60 v ssa analog ground 295.85 -2311.60 sp+ speaker positive 629.45 -2311.60 v cca analog supply voltage 963.05 -2311.60 v cca analog supply voltage 1053.05 -2311.60 ana in analog input 1260.35 -2311.60 aux in auxiliary input 1525.95 -2311.60 aux out auxiliary output 1770.15 -2311.60
isd5100 series publication release date: may 16, 2007 - 85 - revision 1.4 12.8 isd5102 d ie i nformation isd5102 v ssa mic + mic - ana out + ana out - acap sp - v ssa [2] sp + v cca [2] ana in aux in aux out v ssd v ssd a0 sda a1 scl v ccd xclk rac v ssa int v ccd isd5102 device die dimensions (include scribe line) x: 4230 i y: 5046 i die thickness [3] 292.1 i ? 12.7 i pad opening single pad: 90 x 90 i double pad: 180 x 90 i notes 1. the backside of die is internally connected to vss. it must not be connected to any other potential or damage may occur. 2. double bond recommended, if treated as single doubled-pad. 3. this figure reflects the current die thickness. pl ease contact winbond as this thickness may change in the future.
isd5100 series - 86 - isd5102 pad coordinates (with respect to die center in m) pad pad name x axis y axis v ssa analog ground 1882.4 2306.65 rac row address clock 1539.15 2306.65 int interrupt 790.35 2306.65 xclk external clock input 478.55 2306.65 v ccd digital supply voltage 291.55 2306.65 v ccd digital supply voltage 76.15 2306.65 scl serial clock line -198.45 2306.65 a1 address 1 -557.95 2306.65 sda serial data address -815.25 2306.65 a0 address 0 -1366.45 2306.65 v ssd digital ground -1839.95 2306.65 v ssd digital ground -1668.35 2306.65 v ssa analog ground -1945.05 -2311.60 mic+ non-inverting microphone input -1739.25 -2311.60 mic- inverting microphone input -1506.75 -2311.60 ana out+ non-inverting analog output -1245.05 -2311.60 ana out- inverting analog output -910.85 -2311.60 acap agc/automute cap -623.55 -2311.60 sp- speaker negative -127.75 -2311.60 v ssa analog ground 205.85 -2311.60 v ssa analog ground 295.85 -2311.60 sp+ speaker positive 629.45 -2311.60 v cca analog supply voltage 963.05 -2311.60 v cca analog supply voltage 1053.05 -2311.60 ana in analog input 1260.35 -2311.60 aux in auxiliary input 1525.95 -2311.60 aux out auxiliary output 1770.15 -2311.60
isd5100 series publication release date: may 16, 2007 - 87 - revision 1.4 13. ordering information winbond part number description when ordering the devices, please refer to the following valid ordering numbers. for the shaded part numbers, please contact th e local winbond sales repres entatives for availability. duration isd5102 isd5104 isd5108 isd5116 type package part # order # part # order # part # order # part # order # die isd5102x i5102x isd5104x i5104x isd5108x i5108x isd5116x i5116x pdip n/a n/a n/a n/a n/a n/a ISD5116PY i5116py isd5102sy i5102sy isd5104sy i5104 sy isd5108sy i5108sy isd5116sy i5116sy soic isd5102syi i5102syi isd5104syi i5104sy i isd5108syi i5108syi isd5116syi i5116syi isd5102ey i5102ey isd5104ey i5104 ey isd5108ey i5108ey isd5116ey i5116ey lead-free tsop isd5102eyi i5102eyi isd5104eyi i5104ey i isd5108eyi i5108eyi isd5116eyi i5116eyi for the latest product information, access winbond?s worldwide website at http://www.winbond-usa.com lead-free : y = lead-free product series isd5100-series isd 5 1 duration : 02 = 1 to 2 min 04 = 2 to 4 min 08 = 4 to 8 min 16 = 8 to 16 min } } temperature : blank = commercial packaged (0c to +70c) or commercial die (0c to +50c) i = industrial (?40c to +85c) package type : x = die p = 28-lead 600-mil plastic dual inline package (pdip) s = 28-lead 300-mil plastic small outline package (soic) e = 28-lead 8x13.4mm plastic thin small outline package (tsop) type 1
isd5100 series - 88 - 14. version history version date description 0.1 mar 2003 new data sheet for the isd5100-series 0.2 oct 2003 add i5102 and i5104 products utilize tad application in functional details reserve load address feature for factory uses simplify playback mode anain: add k for ra & rb auxin: add k for ra & rb, remove duplicate diagram, correct parameter names in gain setting table & fix typos add application diagram add pcb layout example for tsop package i 2 c protocol: revise r/w bit =1 for reading status packaging: revise unit to mil instead of inch for soic & pdip fix other typos 1.0 jul 2004 vcc: industrial temp: 2.7 ? 3.3v (5108: 2.7- 3.6v) section 7.3.10 cfg0: select 8 speaker output section 7.6.2 auxout: correct parameter name to opa1 application diagram: revise pin # on sda & a1 1.1 nov 2004 revise operating conditions sections add pb-free option to ordering info 1.2 apr 2005 revise ordering info section update disclaim section 1.3 oct. 2005 revise packaging information. 1.4 may. 2007 remove leaded package offer update xclk description revise application diagram
isd5100 series publication release date: may 16, 2007 - 89 - revision 1.4 winbond products are not designed, intended, authorized or wa rranted for use as components in systems or equipment intended for surgical implantation, atomic energy control inst ruments, airplane or spaceshi p instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in su ch applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the contents of this document are provided only as a guide for the applications of winbond products. winbond makes no representation or warranties with respect to the accuracy or completeness of the cont ents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. no license, whether express or implied, to any intellectual pr operty or other right of winbond or others is granted by this publication. except as set forth in winbond's standard terms and conditions of sale, winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any intellectual property. the contents of this document are provided ?as is?, and winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any intellectual property. in no event, shall winbond be liable for any damages whatsoever (including, without limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if winbond has been advised of the possibility of such damages. application examples and alternative uses of any integrated ci rcuit contained in this publication are for illustration only and winbond makes no representation or warranty that such applications shall be suitable for the use specified. the 100-year retention and 100k record cycle projections ar e based upon accelerated reliability tests, as published in the winbond reliability report, and are neither warranted no r guaranteed by winbond. this product incorporates superflash ? . information contained in this isd ? chipcorder ? datasheet supersedes all data for the isd chipcorder products published by isd ? prior to august, 1998. this datasheet and any future addendum to this datasheet is(are) the complete and controlling isd ? chipcorder ? product specifications. in the event any inconsistencie s exist between the information in this and other product documentation, or in the event that other product documentati on contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. this datasheet is subject to change without notice. copyright ? 2005, winbond electronics corporation. all rights reserved. chipcorder ? and isd ? are trademarks of winbond electronics corporation. superflash ? is the trademark of silicon storage technology, inc. all other trademarks are properties of their respective owners.

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